component
SN74HC374PW
Public Made by Adomby adom
lingxingic Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC374PW
lingxingic · Flip Flops · TSSOP-20
SN74HC374PW from lingxingic, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable; when high, outputs Q0 to Q7 go to high impedance (Z) without changing the stored register state. |
| 2 | Q0 | tri_state | Three-state, non-inverting data output of flip-flop 0; high impedance while OE is high. |
| 3 | D0 | input | Data input to flip-flop 0, which must meet the setup and hold times relative to the rising edge of CP. |
| 4 | D1 | input | Data input to flip-flop 1, which must meet the setup and hold times relative to the rising edge of CP. |
| 5 | Q1 | tri_state | Three-state, non-inverting data output of flip-flop 1; high impedance while OE is high. |
| 6 | Q2 | tri_state | Three-state, non-inverting data output of flip-flop 2; high impedance while OE is high. |
| 7 | D2 | input | Data input to flip-flop 2, which must meet the setup and hold times relative to the rising edge of CP. |
| 8 | D3 | input | Data input to flip-flop 3, which must meet the setup and hold times relative to the rising edge of CP. |
| 9 | Q3 | tri_state | Three-state, non-inverting data output of flip-flop 3; high impedance while OE is high. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; the flip-flops capture D on the low-to-high (rising) clock edge. |
| 12 | Q4 | tri_state | Three-state, non-inverting data output of flip-flop 4; high impedance while OE is high. |
| 13 | D4 | input | Data input to flip-flop 4, which must meet the setup and hold times relative to the rising edge of CP. |
| 14 | D5 | input | Data input to flip-flop 5, which must meet the setup and hold times relative to the rising edge of CP. |
| 15 | Q5 | tri_state | Three-state, non-inverting data output of flip-flop 5; high impedance while OE is high. |
| 16 | Q6 | tri_state | Three-state, non-inverting data output of flip-flop 6; high impedance while OE is high. |
| 17 | D6 | input | Data input to flip-flop 6, which must meet the setup and hold times relative to the rising edge of CP. |
| 18 | D7 | input | Data input to flip-flop 7, which must meet the setup and hold times relative to the rising edge of CP. |
| 19 | Q7 | tri_state | Three-state, non-inverting data output of flip-flop 7; high impedance while OE is high. |
| 20 | VCC | power_in | Supply voltage; absolute maximum 7.0 V and recommended range 2.0 V to 6.0 V for the SN74HC374. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute max) | VCC | -0.5 | 7 | V | 6 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 6 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 6 | |
| Output current | IO | -35 | 35 | mA | -0.5V<VO<VCC+0.5V | 6 | |
| Supply current (absolute max) | ICC | 70 | mA | 6 | |||
| Ground current | IGND | -70 | mA | 6 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 6 | ||
| Total power dissipation | Ptot | 500 | mW | 6 | |||
| Soldering temperature | TL | 260 | ℃ | 10秒; SOP/TSSOP/SOP(M) | 6 | ||
| Supply voltage (recommended, SN74HC374) | VCC | 2 | 5 | 6 | V | 7 | |
| Input voltage (recommended) | VI | 0 | V | 7 | |||
| Output voltage (recommended) | VO | 0 | V | 7 | |||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 7 | ||
| High-level input voltage | VIH | 1.5 | V | Tamb=-40~125℃; VCC=2.0V | 8 | ||
| High-level input voltage | VIH | 3.15 | V | Tamb=-40~125℃; VCC=4.5V | 8 | ||
| High-level input voltage | VIH | 4.2 | V | Tamb=-40~125℃; VCC=6.0V | 8 | ||
| Low-level input voltage | VIL | 0.5 | V | Tamb=-40~125℃; VCC=2.0V | 8 | ||
| Low-level input voltage | VIL | 1.35 | V | Tamb=-40~125℃; VCC=4.5V | 8 | ||
| Low-level input voltage | VIL | 1.8 | V | Tamb=-40~125℃; VCC=6.0V | 8 | ||
| High-level output voltage | VOH | 1.9 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=-20uA；VCC=2.0V | 8 | ||
| High-level output voltage | VOH | 4.4 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=-20uA；VCC=4.5V | 8 | ||
| High-level output voltage | VOH | 5.9 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=-20uA；VCC=6.0V | 8 | ||
| High-level output voltage | VOH | 3.7 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=-6.0mA；VCC=4.5V | 8 | ||
| High-level output voltage | VOH | 5.2 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=-7.8mA；VCC=6.0V | 8 | ||
| Low-level output voltage | VOL | 0.1 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=20uA；VCC=2.0V | 8 | ||
| Low-level output voltage | VOL | 0.4 | V | Tamb=-40~125℃; VI=VIH或VIL；IO=6.0mA；VCC=4.5V | 8 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=-40~125℃; VI=VCC或GND；VCC=6.0V | 8 | |
| Off-state output current | IOZ | -10 | 10 | uA | Tamb=-40~125℃; VI=VIH或VIL；VCC=6.0V；VO=VCC或GND | 8 | |
| Quiescent supply current | ICC | 160 | uA | Tamb=-40~125℃; VI=VCC或GND；IO=0A；VCC=6.0V | 8 | ||
| Propagation delay CP to Qn | tpd | 250 | ns | Tamb=-40~125℃; 见图6; VCC=2.0V | 12 | ||
| Propagation delay CP to Qn | tpd | 50 | ns | Tamb=-40~125℃; 见图6; VCC=4.5V | 12 | ||
| Propagation delay CP to Qn | tpd | 43 | ns | Tamb=-40~125℃; 见图6; VCC=6.0V | 12 | ||
| Enable time OE to Qn | ten | 225 | ns | Tamb=-40~125℃; 见图7; VCC=2.0V | 12 | ||
| Enable time OE to Qn | ten | 45 | ns | Tamb=-40~125℃; 见图7; VCC=4.5V | 12 | ||
| Enable time OE to Qn | ten | 38 | ns | Tamb=-40~125℃; 见图7; VCC=6.0V | 12 | ||
| Disable time OE to Qn | tdis | 225 | ns | Tamb=-40~125℃; 见图7; VCC=2.0V | 12 | ||
| Disable time OE to Qn | tdis | 45 | ns | Tamb=-40~125℃; 见图7; VCC=4.5V | 12 | ||
| Disable time OE to Qn | tdis | 38 | ns | Tamb=-40~125℃; 见图7; VCC=6.0V | 12 | ||
| Output transition time Qn | tt | 90 | ns | Tamb=-40~125℃; Qn输出; 见图6; VCC=2.0V | 12 | ||
| Output transition time Qn | tt | 18 | ns | Tamb=-40~125℃; Qn输出; 见图6; VCC=4.5V | 12 | ||
| Output transition time Qn | tt | 15 | ns | Tamb=-40~125℃; Qn输出; 见图6; VCC=6.0V | 12 | ||
| CP pulse width (high or low) | tW | 120 | ns | Tamb=-40~125℃; 见图6; VCC=2.0V | 12 | ||
| CP pulse width (high or low) | tW | 24 | ns | Tamb=-40~125℃; 见图6; VCC=4.5V | 12 | ||
| CP pulse width (high or low) | tW | 20 | ns | Tamb=-40~125℃; 见图6; VCC=6.0V | 12 | ||
| Data Dn to CP setup time | tsu | 90 | ns | Tamb=-40~125℃; 见图6; VCC=2.0V | 12 | ||
| Data Dn to CP setup time | tsu | 18 | ns | Tamb=-40~125℃; 见图6; VCC=4.5V | 12 | ||
| Data Dn to CP setup time | tsu | 15 | ns | Tamb=-40~125℃; 见图6; VCC=6.0V | 12 | ||
| Data Dn to CP hold time | th | 5 | ns | Tamb=-40~125℃; 见图6; VCC=2.0V | 12 | ||
| Maximum clock frequency fmax | fmax | 4 | MHz | Tamb=-40~125℃; CP输入; 见图6; VCC=2.0V | 12 | ||
| Maximum clock frequency fmax | fmax | 20 | MHz | Tamb=-40~125℃; CP输入; 见图6; VCC=4.5V | 12 | ||
| Maximum clock frequency fmax | fmax | 24 | MHz | Tamb=-40~125℃; CP输入; 见图6; VCC=6.0V | 12 |
CAD (KiCad official)
- Symbol:
SN74HC374PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hc374pw-etched.step/sn74hc374pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc374pw.step/sn74hc374pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (21 pp, sha256
e6d21ba7a671b3e3, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).