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GD32F303CCT6A

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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GD32F303CCT6A

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

GD32F303CCT6A from GigaDevice Semicon Beijing, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Power pin with default function VBAT; the LQFP48 pin table gives no voltage limits for it.
2 PC13-TAMPER-RTC bidirectional Default function PC13; alternate function TAMPER-RTC.
3 PC14-OSC32IN bidirectional Default function PC14; alternate function OSC32IN.
4 PC15-OSC32OUT bidirectional Default function PC15; alternate function OSC32OUT.
5 OSCIN input Default function OSCIN; can be remapped to PD0, which cannot be used for EXTI in this package.
6 OSCOUT output Default function OSCOUT; can be remapped to PD1, which cannot be used for EXTI in this package.
7 NRST bidirectional Default function NRST; no alternate function is listed for this pin in the pin table.
8 VSSA power_in Analog ground pin with default function VSSA; the pin table gives no further limits.
9 VDDA power_in Analog supply pin with default function VDDA; the pin table gives no voltage limits for it.
10 PA0-WKUP bidirectional Default function PA0; alternate functions WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI and TIMER4_CH0.
11 PA1 bidirectional Default function PA1; alternate functions USART1_RTS, ADC012_IN1, TIMER1_CH1 and TIMER4_CH1.
12 PA2 bidirectional Default function PA2; alternate functions USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, SPI0_IO2, and TIMER8_CH0 (available only in GD32F303CG devices per footnote 3).
13 PA3 bidirectional Default function PA3; alternate functions USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, SPI0_IO3, and TIMER8_CH1 (available only in GD32F303CG devices per footnote 3).
14 PA4 bidirectional Default function PA4; alternate functions SPI0_NSS, USART1_CK, ADC01_IN4 and DAC_OUT0; remap to SPI2_NSS and I2S2_WS.
15 PA5 bidirectional Default function PA5; alternate functions SPI0_SCK, ADC01_IN5 and DAC_OUT1.
16 PA6 bidirectional Default function PA6; alternate functions SPI0_MISO, ADC01_IN6, TIMER2_CH0 and TIMER12_CH0 (available only in GD32F303CG devices per footnote 3); remap to TIMER0_BRKIN.
17 PA7 bidirectional Default function PA7; alternate functions SPI0_MOSI, ADC01_IN7, TIMER2_CH1 and TIMER13_CH0 (available only in GD32F303CG devices per footnote 3); remap to TIMER0_CH0_ON.
18 PB0 bidirectional Default function PB0; alternate functions ADC01_IN8 and TIMER2_CH2; remap to TIMER0_CH1_ON.
19 PB1 bidirectional Default function PB1; alternate functions ADC01_IN9 and TIMER2_CH3; remap to TIMER0_CH2_ON.
20 PB2 bidirectional 5 V tolerant pin with default function PB2 and BOOT1.
21 PB10 bidirectional 5 V tolerant pin with default function PB10; alternate functions I2C1_SCL and USART2_TX; remap to TIMER1_CH2.
22 PB11 bidirectional 5 V tolerant pin with default function PB11; alternate functions I2C1_SDA and USART2_RX; remap to TIMER1_CH3.
23 VSS_1 power_in Ground pin with default function VSS_1.
24 VDD_1 power_in Power pin with default function VDD_1; the pin table gives no voltage limits for it.
25 PB12 bidirectional 5 V tolerant pin with default function PB12; alternate functions SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN and I2S1_WS.
26 PB13 bidirectional 5 V tolerant pin with default function PB13; alternate functions SPI1_SCK, USART2_CTS, TIMER0_CH0_ON and I2S1_CK.
27 PB14 bidirectional 5 V tolerant pin with default function PB14; alternate functions SPI1_MISO, USART2_RTS and TIMER0_CH1_ON, plus TIMER11_CH0 (available only in GD32F303CG devices per footnote 3).
28 PB15 bidirectional 5 V tolerant pin with default function PB15; alternate functions SPI1_MOSI, TIMER0_CH2_ON and I2S1_SD, plus TIMER11_CH1 (available only in GD32F303CG devices per footnote 3).
29 PA8 bidirectional 5 V tolerant pin with default function PA8; alternate functions USART0_CK, TIMER0_CH0, CK_OUT0 and CTC_SYNC.
30 PA9 bidirectional 5 V tolerant pin with default function PA9; alternate functions USART0_TX and TIMER0_CH1.
31 PA10 bidirectional 5 V tolerant pin with default function PA10; alternate functions USART0_RX and TIMER0_CH2.
32 PA11 bidirectional 5 V tolerant pin with default function PA11; alternate functions USART0_CTS, CAN0_RX, USBDM and TIMER0_CH3.
33 PA12 bidirectional 5 V tolerant pin with default function PA12; alternate functions USART0_RTS, CAN0_TX, TIMER0_ETI and USBDP.
34 PA13 bidirectional 5 V tolerant pin with default functions JTMS and SWDIO; remap to PA13.
35 VSS_2 power_in Ground pin with default function VSS_2.
36 VDD_2 power_in Power pin with default function VDD_2; the pin table gives no voltage limits for it.
37 PA14 bidirectional 5 V tolerant pin with default functions JTCK and SWCLK; remap to PA14.
38 PA15 bidirectional 5 V tolerant pin with default function JTDI; alternate functions SPI2_NSS and I2S2_WS; remap to TIMER1_CH0, TIMER1_ETI, PA15 and SPI0_NSS.
39 PB3 bidirectional 5 V tolerant pin with default function JTDO; alternate functions SPI2_SCK and I2S2_CK; remap to PB3, TRACESWO, TIMER1_CH1 and SPI0_SCK.
40 PB4 bidirectional 5 V tolerant pin with default function NJTRST; alternate function SPI2_MISO; remap to TIMER2_CH0, PB4 and SPI0_MISO.
41 PB5 bidirectional Default function PB5; alternate functions I2C0_SMBA, SPI2_MOSI and I2S2_SD; remap to TIMER2_CH1 and SPI0_MOSI.
42 PB6 bidirectional 5 V tolerant pin with default function PB6; alternate functions I2C0_SCL and TIMER3_CH0; remap to USART0_TX and SPI0_IO2.
43 PB7 bidirectional 5 V tolerant pin with default function PB7; alternate functions I2C0_SDA and TIMER3_CH1; remap to USART0_RX and SPI0_IO3.
44 BOOT0 input Input pin with default function BOOT0.
45 PB8 bidirectional 5 V tolerant pin with default function PB8; alternate function TIMER3_CH2, plus TIMER9_CH0 (available only in GD32F303CG devices per footnote 3); remap to I2C0_SCL and CAN0_RX.
46 PB9 bidirectional 5 V tolerant pin with default function PB9; alternate function TIMER3_CH3, plus TIMER10_CH0 (available only in GD32F303CG devices per footnote 3); remap to I2C0_SDA and CAN0_TX.
47 VSS_3 power_in Ground pin with default function VSS_3.
48 VDD_3 power_in Power pin with default function VDD_3; the pin table gives no voltage limits for it.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External voltage range VDD -0.3 3.6 V Relative to VSS: VSS - 0.3 to VSS + 3.6 V 51
External analog supply voltage VDDA -0.3 3.6 V Relative to VSSA: VSSA - 0.3 to VSSA + 3.6 V 51
External battery supply voltage VBAT -0.3 3.6 V Relative to VSS: VSS - 0.3 to VSS + 3.6 V 51
Input voltage on 5V tolerant pin VIN -0.3 V Min VSS - 0.3 V; max printed as VDD + 3.6 V; VIN max cannot exceed 5.5 V 51
Input voltage on other I/O VIN -0.3 3.6 V Relative to VSS 51
Variations between different VDD power pins /ΔVDDX/ 50 mV 51
Variations between different ground pins /VSSX −VSS/ 50 mV 51
Maximum current for GPIO pins IIO -25 25 mA Printed ±25 mA 51
Operating temperature range TA -40 85 °C 51
Power dissipation at TA = 85°C of LQFP48 PD 621 mW TA = 85 °C, LQFP48 51
Storage temperature range TSTG -65 150 °C 51
Maximum junction temperature TJ 125 °C 51
Supply voltage VDD 2.6 3.3 3.6 V 51
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 51
Battery supply voltage VBAT 1.8 3.6 V 51
AHB clock frequency fHCLK 120 MHz 52
APB1 clock frequency fAPB1 60 MHz 52
APB2 clock frequency fAPB2 120 MHz 52
Crystal or ceramic frequency fHXTAL 4 8 32 MHz 2.6 V ≤ VDD ≤ 3.6 V 63
Recommended matching capacitance on OSCIN and OSCOUT CHXTAL 20 30 pF 63
Crystal or ceramic duty cycle Ducy(HXTAL) 30 50 70 % 63
External clock source or oscillator frequency (bypass) fHXTAL_ext 1 50 MHz VDD = 3.3 V 63
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -2.5 2.5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 65
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -1.8 1.8 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 65
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25 °C 65
Low Speed Internal oscillator (IRC40K) frequency fIRC40K 20 40 45 kHz VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C 66
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -4 5 % VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C 66
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -3 3 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 66
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -2 2 % VDD = VDDA = 3.3 V, TA = 25 °C 66
PLL input clock frequency fPLLIN 1 25 MHz 67
PLL output clock frequency fPLLOUT 16 120 MHz 67
PLL VCO output clock frequency fVCO 32 240 MHz 67
PLL lock time tLOCK 300 μs 67
Number of guaranteed program /erase cycles before failure (Endurance) PECYC 100 kcycles TA = -40 °C ~ +85 °C 67
Word programming time tPROG 47.5 215 μs TA = -40°C ~ +85 °C 67
Page erase time tERASE 45 800 ms TA = -40°C ~ +85 °C 67
Mass erase time (256K) tMERASE(256K) 2 24 s TA = -40°C ~ +85 °C 67
NRST Input low level voltage VIL(NRST) -0.3 V 2.6 V ≤ VDD = VDDA ≤ 3.6 V; max printed as 0.3 VDD 68
NRST Input high level voltage VIH(NRST) 0.7 xVDD Min 0.7 VDD; max printed as VDD + 0.3 V 68
Standard IO Low level input voltage VIL 0.3 xVDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 69
5V-tolerant IO Low level input voltage VIL 0.3 xVDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 69
Standard IO Low level input voltage (printed under VIH) VIH 0.7 xVDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 69
5V-tolerant IO Low level input voltage (printed under VIH) VIH 0.7 xVDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 69
Low level output voltage for an IO Pin VOL 0.17 V IIO = +8mA, VDD = 2.6 V 69
Low level output voltage for an IO Pin VOL 0.16 V IIO = +8mA, VDD = 3.3 V 69
Low level output voltage for an IO Pin VOL 0.15 V IIO = +8mA, VDD = 3.6 V 69
Low level output voltage for an IO Pin VOL 0.49 V IIO = +20mA, VDD = 2.6 V 69
Low level output voltage for an IO Pin VOL 0.4 V IIO = +20mA, VDD = 3.3 V 69
Low level output voltage for an IO Pin VOL 0.34 V IIO = +20mA, VDD = 3.6 V 69
High level output voltage for an IO Pin VOH 2.4 V IIO = +8mA, VDD = 2.6 V 69
High level output voltage for an IO Pin VOH 3.15 V IIO = +8mA, VDD = 3.3 V 69
High level output voltage for an IO Pin VOH 3.44 V IIO = +8mA, VDD = 3.6 V 69
High level output voltage for an IO Pin VOH 2.02 V IIO = +20mA, VDD = 2.6 V 69
High level output voltage for an IO Pin VOH 2.8 V IIO = +20mA, VDD = 3.3 V 69
Internal pull-up resistor RPU 30 40 50 kΩ All pins VIN = VSS 69
Internal pull-down resistor RPD 30 40 50 kΩ All pins VIN = VDD 69
Electrostatic discharge voltage (human body model) VESD(HBM) 4000 V TA = 25 °C; JS-001-2017 63
Electrostatic discharge voltage (charge device model) VESD(CDM) 750 V TA = 25 °C; JS-002-2018 63
Static latch-up I-test LU -200 200 mA TA = 25 °C; JESD78 63

CAD (KiCad official)

  • Symbol: GD32F303CCT6A
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: gd32f303cct6a-etched.step / gd32f303cct6a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f303cct6a.step / gd32f303cct6a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (99 pp, sha256 98e6e299f43ef5ac, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF