TLV320AIC3101IRHBT from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MCLK	input	Master clock input for the device.
2	BCLK	bidirectional	Audio serial data bus bit clock input/output.
3	WCLK	bidirectional	Audio serial data bus word clock input/output.
4	DIN	input	Audio serial data bus data input.
5	DOUT	output	Audio serial data bus data output.
6	DVSS	power_in	Digital core and I/O ground supply, 0 V.
7	IOVDD	power_in	Digital I/O voltage supply, 1.1 V to 3.6 V.
8	SCL	bidirectional	I2C serial clock input.
9	SDA	bidirectional	I2C serial data input/output.
10	MIC1LP/LINE1LP	input	Left input 1 (single-ended) or left input positive (differential).
11	MIC1LM/LINE1LM	input	Left input negative, differential only.
12	MIC1RP/LINE1RP	input	Right input 1 (single-ended) or right input positive (differential).
13	MIC1RM/LINE1RM	input	Right input negative, differential only.
14	MIC2L/LINE2L/MICDET	input	Left input 2 (single-ended); can support microphone detection.
15	MICBIAS	output	Microphone bias voltage output.
16	MIC2R/LINE2R	input	Right input 2 (single-ended).
17	AVSS1	power_in	Analog ADC ground supply, 0 V.
18	DRVDD	power_in	Analog ADC and output driver voltage supply, 2.7 V to 3.6 V.
19	HPLOUT	output	High-power output driver, left positive (+).
20	HPLCOM	output	High-power output driver, left negative (-) or multifunctional.
21	DRVSS	power_in	Analog output driver ground supply, 0 V.
22	HPRCOM	output	High-power output driver, right negative (-) or multifunctional.
23	HPROUT	output	High-power output driver, right positive (+).
24	DRVDD	power_in	Analog output driver voltage supply, 2.7 V to 3.6 V.
25	AVDD	power_in	Analog DAC voltage supply, 2.7 V to 3.6 V.
26	AVSS2	power_in	Analog DAC ground supply, 0 V.
27	LEFT_LOP	output	Left line output (+).
28	LEFT_LOM	output	Left line output (-).
29	RIGHT_LOP	output	Right line output (+).
30	RIGHT_LOM	output	Right line output (-).
31	RESET	input	Device reset input.
32	DVDD	power_in	Digital core voltage supply, 1.525 V to 1.95 V.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32(5x5)
Category	Communication Interface Chip/UART/485/232
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
AVDD to AVSS, DRVDD to DRVSS		-0.3		3.9	V		6
AVDD to DRVSS		-0.3		3.9	V		6
Input voltage IOVDD to DVSS		-0.3		3.9	V		6
DVDD to DVSS		-0.3		2.5	V		6
AVDD to DRVDD		-0.1		0.1	V		6
Digital input voltage to DVSS		-0.3			V		6
Analog input voltage to AVSS		-0.3			V		6
Operating temperature		-40		85	°C		6
Junction temperature	TJ			105	°C		6
Storage temperature	Tstg	-65		105	°C		6
Power dissipation				0.5	W		6
Analog supply voltage (AVDD, DRVDD1/2)	AVDD, DRVDD1/2	2.7	3.3	3.6	V		6
Digital core supply voltage	DVDD	1.525	1.8	1.95	V		6
Digital I/O supply voltage	IOVDD	1.1	1.8	3.6	V		6
Operating free-air temperature	TA	-40		85	°C		6
RθJA Junction-to-ambient thermal resistance	RθJA		32.1		°C/W	RHB 32 pins	7
RθJC(top) Junction-to-case (top) thermal resistance	RθJC(top)		23		°C/W	RHB 32 pins	7
RθJB Junction-to-board thermal resistance	RθJB		6		°C/W	RHB 32 pins	7
ψJT Junction-to-top characterization parameter	ψJT		0.3		°C/W	RHB 32 pins	7
ψJB Junction-to-board characterization parameter	ψJB		6		°C/W	RHB 32 pins	7
RθJC(bot) Junction-to-case (bottom) thermal resistance	RθJC(bot)		1.4		°C/W	RHB 32 pins	7
ADC programmable-gain amplifier maximum gain				59.5	dB	1-kHz input tone	7
Input level control minimum		0			dB		7
Input level control maximum				12	dB		7
Filter gain, from 0 to 0.39 fS (tolerance)		-0.1		0.1	dB	From 0 to 0.39 fS	8
Microphone bias voltage (programmable setting 2.5 V)		2.3	2.455	2.7	V	Programmable setting = 2.5 V	8
Maximum programmable output level control gain				9	dB		9
DAC digital interpolation filter pass-band ripple		-0.06		0.06	dB		9
DAC digital interpolation filter pass band		0			Hz		9
Digital I/O input low level	VIL	-0.3			V		10
Digital I/O input high level	VIH	1.1			V	IOVDD ≤ 1.6 V	10
AVDD to DVDD power-up sequencing delay	t2	0		5	ms		88

CAD (KiCad official)

Symbol: TLV320AIC3101IRHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
3D model files: tlv320aic3101irhbt-etched.step / tlv320aic3101irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv320aic3101irhbt.step / tlv320aic3101irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (99 pp, sha256 4b9d4b2a9c1f508a, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TLV320AIC3101IRHBT

Verified TLV320AIC3101IRHBT

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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