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Contents

README

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TPS62134DRGTR

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TPS62134DRGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOS input Output voltage sense pin for the control loop circuitry, which must be connected directly at the output capacitor.
2 SW power_out Switch node connected to the internal MOSFET switches; connect the inductor between this pin and the output capacitor.
3 SW power_out Switch node connected to the internal MOSFET switches; connect the inductor between this pin and the output capacitor.
4 PG output Open-drain power-good output that requires a pullup resistor (V(PG) 0 to 6 V, sink current max 2 mA); leave floating if not used.
5 FBS input Output-voltage feedback pin used for positive remote sense of the load voltage; must be connected close to the load-supply node on the output bus.
6 AGND power_in Analog ground that must be connected directly to the exposed thermal pad and common ground plane.
7 SS output Soft-start pin; an external capacitor connected to this pin sets the soft-start time.
8 VID1 input Output-voltage selection pin (VIDx) for selecting the fixed output voltage and dynamic output-voltage change.
9 VID0 input Output-voltage selection pin (VIDx) for selecting the fixed output voltage and dynamic output-voltage change.
10 AVIN input Supply-voltage pin for the internal control circuitry; connect to the same source as PVIN, with an input range of 3 V to 17 V.
11 PVIN power_in Supply-voltage pin for the internal power stage, with an input range of 3 V to 17 V.
12 PVIN power_in Supply-voltage pin for the internal power stage, with an input range of 3 V to 17 V.
13 EN input Enable and disable input with an internal pulldown that holds the logic level low if the pin is floating.
14 LPM input Low-power-mode input pin that reduces the output voltage when used to enter low-power mode.
15 PGND power_in Power ground that must be connected directly to the exposed thermal pad and common ground plane.
16 PGND power_in Power ground that must be connected directly to the exposed thermal pad and common ground plane.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Power Supply Chip
Pins 17

CAD (KiCad official)

  • Symbol: TPS62134DRGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps62134drgtr-etched.step / tps62134drgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62134drgtr.step / tps62134drgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 025c93b0451bd3e1, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF