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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS53632GRSMR

Texas Instruments · AC-DC Controllers And Regulators · VQFN-32(4x4)

TPS53632GRSMR from Texas Instruments, in a VQFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Serial digital I/O line of the I2C interface, with recommended voltage range of -0.1 V to 3.5 V.
2	VDD	power_in	3.3-V digital power input that must be bypassed to GND with a capacitor of at least 1 µF and operates from 3.1 V to 3.5 V.
3	PGOOD	output	Open-drain power good output, with recommended voltage range of -0.1 V to 3.5 V.
4	NC	unconnected	No connect.
5	PWM-LO	output	PWM control output for the external low-side driver at 5-V logic level, which the controller forces to the tri-state level when needed.
6	PWM-HI	output	PWM control output for the external high-side driver at 5-V logic level, which the controller forces to the tri-state level when needed.
7	SKIP	output	When high, the driver enters FCCM mode, otherwise DCM mode; driving the tri-state level puts the drivers into a low-power sleep mode.
8	EN	input	Enable input with 100-ns de-bounce; when brought low the regulator enters low-power mode but retains start-up settings.
9	PU	input	Pull-up to VREF through a 10-kΩ resistor.
10	FREQ-P	input	A resistor between this pin and GND sets the per-phase switching frequency, and a resistor to VREF disables dynamic phase add and drop operation.
11	RAMP	input	Voltage divider to VREF where a resistor to GND sets the ramp setting voltage, which can override the factory ramp setting.
12	OCP-I	bidirectional	Voltage divider to IMON whose resistor ratio sets the IMON gain, and a resistor to GND (ROCP) selects one of 8 per-phase OCP levels latched at start-up.
13	IMON	output	Analog current monitor output following VIMON = ΣVISENSE × (1 + RIMON/ROCP).
14	VINTF	power_in	Input voltage to the interface logic, which can be between 1.62 V and 3.5 V.
15	SLEWA	input	The voltage sets the 3 LSBs of the I2C address and the resistance to GND selects one of 8 slew rates, with ADDRESS and SLEWRATE latched at start-up.
16	VBUS	power_in	Provides input voltage information to the on-time circuits for both converters, with recommended range of -0.1 V to 28 V and absolute maximum of 30 V.
17	CSP1	input	Positive current sense input connected to the most positive node of the current sense resistor or inductor DCR network; tie CSP2 or CSP1 (in that order) to a 3.3-V supply to disable the CSP2 phase.
18	CSN1	input	Negative current sense input connected to the most negative node of the current sense resistor or inductor DCR network, which also has a secondary OVP comparator.
19	CSN2	input	Negative current sense input for phase 2, connected to the most negative node of the current sense resistor or inductor DCR network.
20	CSP2	input	Positive current sense input for phase 2, connected to the most positive node of the current sense resistor or inductor DCR network, and tied to a 3.3-V supply to disable this phase.
21	PU3	power_in	Connect to a 3.3-V supply.
22	NC	unconnected	No connect.
23	GFB	input	Voltage sense return that is tied to GND on the PCB through a 10-Ω resistor when the microprocessor is not populated, with absolute range of -0.2 V to 0.2 V.
24	VFB	input	Voltage sense line tied directly to the processor VOUT sense point, with more than 1 MΩ required between VFB and GFB and absolute maximum of 3.6 V.
25	DROOP	output	Error amplifier output where a resistor pair to VREF and to COMP sets the droop gain, ADROOP = 1 + RDROOP / RCOMP.
26	COMP	input	Error amplifier summing node where resistors RCOMP (to VREF) and RDROOP (to DROOP) set the droop gain.
27	VREF	power_in	1.7-V, 500-µA reference that must be bypassed to GND with a 0.22-µF ceramic capacitor.
28	V5A	power_in	5-V analog power input, connected through a resistor to the 5-V plane and bypassed to GND with at least 1 µF ceramic, operating from 4.5 V to 5.5 V.
29	GND	power_in	Analog circuit reference that should be tied to a quiet point on the ground plane.
30	NC	unconnected	No connect.
31	SCL	input	Serial digital clock line of the I2C interface, with recommended voltage range of -0.1 V to 3.5 V.
32	NC	unconnected	No connect.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32(4x4)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: TPS53632GRSMR
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32(4x4) (KiCad packages3D, STEP)
3D model files: tps53632grsmr-etched.step / tps53632grsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53632grsmr.step / tps53632grsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (42 pp, sha256 2763a5aa2352d309, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF