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vpc2842

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by Ray

VPSC DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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VPC2842

VPSC · DC-DC Converters · SOP-8

VPC2842 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error-amplifier output / loop compensation pin. Connect external compensation network to this pin to shape the EA output; the EA is internally current-limited so pulling COMP to GND externally forces zero duty cycle. Typical VOH ≈ 6 V, VOL ≈ 0.1 V (with RCOMP = 15 kΩ).
2 FB input Inverting input of the internal error amplifier. Used to close the converter voltage-feedback loop; the internal non-inverting reference is 2.5 V (±1%). Keep trace short and stray capacitance minimal for stability.
3 CS input Primary-side current-sense input to the PWM comparator. Connect to the current-sense resistor; PWM terminates the OUT on-pulse when VCS reaches the internal threshold (typ. 1.0 V, max 1.1 V). Current-sense amp gain ≈ 3 V/V; can also accept a voltage ramp for voltage-mode operation or slope compensation. CS→OUT delay ≈ 30 ns.
4 RT/CT passive Fixed-frequency oscillator timing pin. RT from VREF to this pin sets the charging current; CT from this pin to GND sets the ramp. Frequency estimated by fOSC = 1.6 / (RT × CT). Recommended RT range 5 kΩ-100 kΩ, CT 1 nF-100 nF. Oscillator ramp p-p ≈ 1.6 V; discharge current typ. 8.3 mA.
5 GND power_in Analog ground. For packages without a separate PGND (SOP-8), this pin also serves as the power ground return. Keep signal-return and gate-driver return paths separated on the PCB.
6 OUT output Push-pull totem-pole gate-drive output for the external power MOSFET. Sources and sinks up to ±1 A peak; rail-to-rail (RDSON typ. 8 Ω pull-up, 4 Ω pull-down); tr ≈ 30 ns / tf ≈ 20 ns into 1 nF. Held low when VDD is below the turn-on threshold; a Schottky clamp to GND is recommended to suppress undershoot.
7 VDD power_in Analog controller bias supply. Recommended operating range up to 28 V (absolute max 30 V). IST < 100 µA before VDD(ON) = 14.6 V typ.; quiescent IVDD ≈ 2.7 mA after startup. UVLO turn-off 8.7 V typ. Internal clamp begins to conduct near 19 V and reaches ~14 mA at 24.7 V - use a series limiting resistor from the auxiliary winding to prevent VDD overvoltage. Bypass with 0.1 µF ceramic close to the pin plus additional bulk capacitance ≥10× the external MOSFET gate capacitance.
8 VREF power_out 5.0 V (±2%) precision reference output derived by an internal LDO from VDD. Supplies the RT charging current and can drive external loads up to 20 mA (short-circuit ISC ≈ -50 mA). Must be bypassed with a ≥0.1 µF ceramic capacitor close to the pin for reference stability; held low while VDD is below UVLO, so VREF can act as a power-good logic indicator.

Key specifications

Parameter Value
Manufacturer VPSC
Package SOP-8
Category PMIC
Pins 8

Ordering variants

  • VPC2842
  • VPC2842VPC2843
  • VPC2842VPC2844
  • VPC2842VPC2845
  • VPC2842VPC3842
  • VPC2842VPC3843
  • VPC2842VPC3844
  • VPC2842VPC3845

CAD (KiCad official)

  • Symbol: VPC2842
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VPSC datasheet (None pp, sha256 0a541837a1512dc8, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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Datasheet

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