component
CD4516BE
Public Made by Adomby adom
Texas Instruments Counters / Dividers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4516BE
Texas Instruments · Counters / Dividers · PDIP-16
CD4516BE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PRESET ENABLE | input | A high level on this line presets the counter to the number present on the jam inputs P1-P4. |
| 2 | Q4 | output | Buffered Q4 counter output, the fourth flip-flop output. |
| 3 | P4 | input | Jam (preset) input 4, loaded into the counter when PRESET ENABLE is high. |
| 4 | P1 | input | Jam (preset) input 1, loaded into the counter when PRESET ENABLE is high. |
| 5 | CARRY IN | input | Active-low carry input; when held low the counter advances up or down on each positive-going clock transition. |
| 6 | Q1 | output | Buffered Q1 counter output, the first flip-flop output. |
| 7 | CARRY OUT | output | Active-low carry output, connected to CARRY IN of the next more significant stage for synchronous cascading or to the clock for ripple cascading. |
| 8 | VSS | power_in | Ground (negative supply) terminal; the supply voltage range is referenced to it. |
| 9 | RESET | input | A high level on this line clears the counter. |
| 10 | UP/DOWN | input | Count direction control input for up or down counting. |
| 11 | Q2 | output | Buffered Q2 counter output, the second flip-flop output. |
| 12 | P2 | input | Jam (preset) input 2, loaded into the counter when PRESET ENABLE is high. |
| 13 | P3 | input | Jam (preset) input 3, loaded into the counter when PRESET ENABLE is high. |
| 14 | Q3 | output | Buffered Q3 counter output, the third flip-flop output. |
| 15 | CLOCK | input | Clock input; the counter advances on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply terminal; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | Logic ICs |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4516BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4516be-etched.step/cd4516be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4516be.step/cd4516be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
fc185675c565180b, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).