component
MSP430F5310IRGCT
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownMSP430F5310IRGCT
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)
MSP430F5310IRGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.0/CB0/A0 | bidirectional | General-purpose digital I/O, Comparator_B input CB0, Analog input A0 for ADC. |
| 2 | P6.1/CB1/A1 | bidirectional | General-purpose digital I/O, Comparator_B input CB1, Analog input A1 for ADC. |
| 3 | P6.2/CB2/A2 | bidirectional | General-purpose digital I/O, Comparator_B input CB2, Analog input A2 for ADC. |
| 4 | P6.3/CB3/A3 | bidirectional | General-purpose digital I/O, Comparator_B input CB3, Analog input A3 for ADC. |
| 5 | P6.4/CB4/A4 | bidirectional | General-purpose digital I/O, Comparator_B input CB4, Analog input A4 for ADC. |
| 6 | P6.5/CB5/A5 | bidirectional | General-purpose digital I/O, Comparator_B input CB5, Analog input A5 for ADC. |
| 7 | P6.6/CB6/A6 | bidirectional | General-purpose digital I/O, Comparator_B input CB6, Analog input A6 for ADC. |
| 8 | P6.7/CB7/A7 | bidirectional | General-purpose digital I/O, Comparator_B input CB7, Analog input A7 for ADC. |
| 9 | P5.0/A8/VeREF+ | bidirectional | General-purpose digital I/O, Analog input A8 for ADC, Input for external reference voltage to ADC. |
| 10 | P5.1/A9/VeREF- | bidirectional | General-purpose digital I/O, Analog input A9 for ADC, Negative terminal for externally provided ADC reference. |
| 11 | AVCC1 | power_in | Analog power supply voltage pin. |
| 12 | P5.4/XIN | bidirectional | General-purpose digital I/O, Input terminal for crystal oscillator XT1. |
| 13 | P5.5/XOUT | bidirectional | General-purpose digital I/O, Output terminal of crystal oscillator XT1. |
| 14 | AVSS1 | power_in | Analog ground supply voltage pin. |
| 15 | DVCC1 | power_in | Digital power supply voltage pin. |
| 16 | DVSS1 | power_in | Digital ground supply voltage pin. |
| 17 | VCORE | power_out | Regulated core power supply output for internal use only with no external current loading. |
| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt, TA0 clock signal TA0CLK input, ACLK output divided by 1, 2, 4, 8, 16, or 32. |
| 19 | P1.1/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR0 capture CCI0A input and compare Out0 output, BSL transmit output. |
| 20 | P1.2/TA0.1 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR1 capture CCI1A input and compare Out1 output, BSL receive input. |
| 21 | P1.3/TA0.2 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR2 capture CCI2A input and compare Out2 output. |
| 22 | P1.4/TA0.3 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR3 capture CCI3A input and compare Out3 output. |
| 23 | P1.5/TA0.4 | bidirectional | General-purpose digital I/O with port interrupt, TA0 CCR4 capture CCI4A input and compare Out4 output. |
| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose digital I/O with port interrupt, TA1 clock signal TA1CLK input, Comparator_B output. |
| 25 | P1.7/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt, TA1 CCR0 capture CCI0A input and compare Out0 output. |
| 26 | P2.0/TA1.1 | bidirectional | General-purpose digital I/O with port interrupt, TA1 CCR1 capture CCI1A input and compare Out1 output. |
| 27 | P2.1/TA1.2 | bidirectional | General-purpose digital I/O with port interrupt, TA1 CCR2 capture CCI2A input and compare Out2 output. |
| 28 | P2.2/TA2CLK/SMCLK | bidirectional | General-purpose digital I/O with port interrupt, TA2 clock signal TA2CLK input, SMCLK output. |
| 29 | P2.3/TA2.0 | bidirectional | General-purpose digital I/O with port interrupt, TA2 CCR0 capture CCI0A input and compare Out0 output. |
| 30 | P2.4/TA2.1 | bidirectional | General-purpose digital I/O with port interrupt, TA2 CCR1 capture CCI1A input and compare Out1 output. |
| 31 | P2.5/TA2.2 | bidirectional | General-purpose digital I/O with port interrupt, TA2 CCR2 capture CCI2A input and compare Out2 output. |
| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose digital I/O with port interrupt, RTC clock output for calibration, DMA external trigger input. |
| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose digital I/O with port interrupt, Slave transmit enable USCI_B0 SPI mode, Clock signal for USCI_A0 SPI and master modes. |
| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O, Slave in master out USCI_B0 SPI mode, I2C data USCI_B0 I2C mode. |
| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O, Slave out master in USCI_B0 SPI mode, I2C clock USCI_B0 I2C mode. |
| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O, Clock signal for USCI_B0 SPI slave mode, Clock output for USCI_B0 SPI master mode, Slave transmit enable USCI_A0 SPI mode. |
| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O, Transmit data USCI_A0 UART mode, Slave in master out USCI_A0 SPI mode. |
| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O, Receive data USCI_A0 UART mode, Slave out master in USCI_A0 SPI mode. |
| 39 | DVSS2 | power_in | Digital ground supply voltage pin. |
| 40 | DVCC2 | power_in | Digital power supply voltage pin. |
| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Slave transmit enable USCI_B1 SPI mode, Clock signal for USCI_A1 SPI and master modes. |
| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Slave in master out USCI_B1 SPI mode, I2C data USCI_B1 I2C mode. |
| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Slave out master in USCI_B1 SPI mode, I2C clock USCI_B1 I2C mode. |
| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Clock signal for USCI_B1 SPI slave mode, Clock output USCI_B1 SPI master mode, Slave transmit enable USCI_A1 SPI mode. |
| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Transmit data USCI_A1 UART mode, Slave in master out USCI_A1 SPI mode. |
| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose digital I/O with reconfigurable port mapping, Default mapping Receive data USCI_A1 UART mode, Slave out master in USCI_A1 SPI mode. |
| 47 | P4.6/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping secondary function, Default mapping no secondary function. |
| 48 | P4.7/PM_NONE | bidirectional | General-purpose digital I/O with reconfigurable port mapping secondary function, Default mapping no secondary function. |
| 49 | VSSU | power_in | Port U ground supply voltage pin. |
| 50 | PU.0 | bidirectional | General-purpose digital I/O controlled by PU control register, supplied by LDOO rail for high-current applications. |
| 51 | NC | unconnected | No connect pin, not used. |
| 52 | PU.1 | bidirectional | General-purpose digital I/O controlled by PU control register, supplied by LDOO rail for high-current applications. |
| 53 | LDOI | power_in | LDO input voltage pin for external 3.3V LDO regulator input. |
| 54 | LDOO | power_out | LDO output voltage pin supplying 3.3V regulated power to Port U and internal circuits. |
| 55 | NC | unconnected | No connect pin, not used. |
| 56 | AVSS2 | power_in | Analog ground supply voltage pin. |
| 57 | P5.2/XT2IN | bidirectional | General-purpose digital I/O, Input terminal for crystal oscillator XT2. |
| 58 | P5.3/XT2OUT | bidirectional | General-purpose digital I/O, Output terminal of crystal oscillator XT2. |
| 59 | TEST/SBWTCK | input | Test mode pin for selecting digital I/O on JTAG pins, Spy-Bi-Wire clock input. |
| 60 | PJ.0/TDO | bidirectional | General-purpose digital I/O, JTAG test data output port. |
| 61 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O, JTAG test data input or test clock input. |
| 62 | PJ.2/TMS | bidirectional | General-purpose digital I/O, JTAG test mode select. |
| 63 | PJ.3/TCK | bidirectional | General-purpose digital I/O, JTAG test clock input. |
| 64 | RST/NMI/SBWTDIO | bidirectional | Reset input active low with internal pullup resistor enabled by default, Nonmaskable interrupt input, Spy-Bi-Wire data input and output. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
MSP430F5310IRGCT - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
msp430f5310irgct-etched.step/msp430f5310irgct-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5310irgct.step/msp430f5310irgct.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (119 pp, sha256
9878fdb58e45d98f, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).