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EFM32PG22C200F64IM40-C

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SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerefm32pg22c200f64im40-cfactory-2.0.0extractor-text

Verified EFM32PG22C200F64IM40-C

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: EFM32PG22C200F64IM40-C · QFN-40(5x5) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 75-page datasheet
  • ✓distributor: lcsc C3226120, digikey 336-EFM32PG22C200F64IM40-C-ND, mouser 634-EFM32PG22C64M40C
  • ✓family: QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zz4_ko08/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.71)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ efm32pg22c200f64im40-c.kicad_sym✓ efm32pg22c200f64im40-c.kicad_mod✓ efm32pg22c200f64im40-c.step
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

EFM32PG22C200F64IM40-C

SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40(5x5)

EFM32PG22C200F64IM40-C from SILICON LABS, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU6.
2 PC01 bidirectional GPIO.
3 PC02 bidirectional GPIO.
4 PC03 bidirectional GPIO.
5 PC04 bidirectional GPIO.
6 PC05 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU7.
7 PC06 bidirectional GPIO.
8 PC07 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU8.
9 HFXTAL_I input High frequency crystal input.
10 HFXTAL_O output High frequency crystal output.
11 RESETn input Reset pin; internally pulled up to DVDD.
12 DVDD power_in Digital power supply.
13 VSS power_in Ground.
14 NC unconnected No-connect.
15 DVDD power_in Digital power supply.
16 PB04 bidirectional GPIO.
17 PB03 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU4.
18 PB02 bidirectional GPIO.
19 PB01 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU3.
20 PB00 bidirectional GPIO.
21 PA00 bidirectional GPIO; can serve as IADC0.VREFP.
22 PA01 bidirectional GPIO; serves as GPIO.SWCLK (debug clock).
23 PA02 bidirectional GPIO; serves as GPIO.SWDIO (debug data).
24 PA03 bidirectional GPIO; alternate functions GPIO.TRACEDATA0, GPIO.SWV and GPIO.TDO.
25 PA04 bidirectional GPIO; alternate functions GPIO.TRACECLK and GPIO.TDI.
26 PA05 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU0.
27 PA06 bidirectional GPIO.
28 PA07 bidirectional GPIO.
29 PA08 bidirectional GPIO.
30 DECOUPLE passive Decouple output for the on-chip voltage regulator; an external decoupling capacitor is required at this pin.
31 VREGSW passive DCDC regulator switching node.
32 VREGVDD power_in DCDC regulator input supply.
33 VREGVSS power_in DCDC ground.
34 DVDD power_in Digital power supply.
35 AVDD power_in Analog power supply.
36 IOVDD power_in I/O power supply.
37 PD03 bidirectional GPIO.
38 PD02 bidirectional GPIO; supports the EM4 wake-up function GPIO.EM4WU9.
39 PD01 bidirectional GPIO; can serve as LFXO.LFXTAL_I or LFXO.LF_EXTCLK.
40 PD00 bidirectional GPIO; can serve as LFXO.LFXTAL_O.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package QFN-40(5x5)
Category Single Chip Microcomputer/Microcontroller
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -50 150 °C 17
Voltage on any supply pin VDDMAX -0.3 3.8 V 17
Junction temperature TJMAX 125 °C -I grade 17
Voltage ramp rate on any supply pin VDDRAMPMAX 1 V / µs 17
Voltage on HFXO pins VHFXOPIN -0.3 1.2 V 17
DC voltage on RESETn pin VRESETn -0.3 3.8 V 17
Total current into VDD power lines IVDDMAX 200 mA Source 17
Total current into VSS ground lines IVSSMAX 200 mA Sink 17
Current per I/O pin (sink) IIOMAX 50 mA Sink 17
Current per I/O pin (source) IIOMAX 50 mA Source 17
Current for all I/O pins (sink) IIOALLMAX 200 mA Sink 17
Current for all I/O pins (source) IIOALLMAX 200 mA Source 17
Operating ambient temperature range TA -40 125 °C -I temperature grade 18
DVDD supply voltage VDVDD 1.71 3 3.8 V EM0/1 18
AVDD supply voltage VAVDD 1.71 3 3.8 V 18
IOVDDx operating supply voltage VIOVDDx 1.71 3 3.8 V All IOVDD pins 18
VREGVDD operating supply voltage VVREGVDD 2.2 3 3.8 V DC-DC in regulation 18
VREGVDD operating supply voltage VVREGVDD 1.8 3 3.8 V DC-DC in bypass 60 mA load 18
VREGVDD operating supply voltage VVREGVDD 1.71 3 3.8 V DC-DC not in use. DVDD externally shorted to VREGVDD 18
DECOUPLE output capacitor CDECOUPLE 1 2.75 µF 1.0 µF ± 10% X8L capacitor used for performance characterization 18
HCLK and SYSCLK frequency fHCLK 76.8 MHz VSCALE2, MODE = WS1 18
HCLK and SYSCLK frequency fHCLK 40 MHz VSCALE2, MODE = WS0 18
PCLK frequency fPCLK 50 MHz VSCALE2 18
PCLK frequency fPCLK 40 MHz VSCALE1 18
External Clock Input fCLKIN 40 MHz VSCALE2 or VSCALE1 18
DPLL Reference Clock fDPLLREFCLK 40 MHz VSCALE2 or VSCALE1 18
Input voltage range at VREGVDD pin VVREGVDD 2.2 3 3.8 V DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode 19
Input voltage range at VREGVDD pin VVREGVDD 1.8 3 3.8 V DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode 19
Regulation DC accuracy ACCDC -2.5 3.3 % VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode 19
Regulation total accuracy ACCTOT -5 7 % With mode transitions between EM0/EM1 and EM2/EM3 modes 19
Output load current ILOAD 60 mA EM0/EM1 mode, DCDC in regulation 19
Output load current ILOAD 5 mA EM2/EM3 mode, DCDC in regulation 19
Nominal output capacitor CDCDC 4.7 10 µF 4.7 µF ± 10% X7R capacitor used for performance characterization 19
Resistance in bypass mode RBYP 1.75 3 Ω Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V 19
Powertrain PFET switch resistance 0.86 1.5 Ω Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V 19
Supply monitor threshold programming range VCMP_RNG 2 2.3 V Programmable in 0.1 V steps 19
Supply monitor threshold accuracy VCMP_ACC -5 5 % Supply falling edge trip point 19
Thermal resistance junction to ambient QFN40 (5x5mm) THETAJA_QFN40_5X5 32.6 °C/W 4-Layer PCB, Natural Convection 22
Flash supply voltage during write or erase VFLASH 1.71 3.8 V 29
Flash erase cycles before failure ECFLASH 10000 cycles 29
Flash data retention RETFLASH 10 years 29
Program time tPROG 42.1 44 45.6 uSec one word (32-bits) 29
Page erase time tPERASE 11.4 12.9 14.4 ms 29
Mass erase time tMERASE 11.7 13 14.3 ms Erases all of User Code area 29
Program current IPROG 1.45 mA 29
Page erase current IPERASE 1.34 mA Page Erase 29
Mass erase current IMERASE 1.28 mA Mass Erase 29
HFRCO frequency accuracy FHFRCO_ACC -3 3 % For all production calibrated frequencies 33
FSRCO frequency FFSRCO 17.2 20 21.2 MHz 34
LFRCO frequency accuracy FLFRCO_ACC -3 3 % 35
ULFRCO oscillation frequency FULFRCO 0.944 1 1.095 kHz 35
Nominal LFRCO oscillation frequency FLFRCO 32.768 kHz 35

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 66

CAD (KiCad official)

  • Symbol: EFM32PG22C200F64IM40-C
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: efm32pg22c200f64im40-c-etched.step / efm32pg22c200f64im40-c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32pg22c200f64im40-c.step / efm32pg22c200f64im40-c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (75 pp, sha256 24858d6bea40dddb, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF