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TPS72301QDBVRQ1
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS72301QDBVRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS72301QDBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin for the regulator. |
| 2 | IN | power_in | Input supply pin, with input voltage range of -2.7 V to -10 V per section 5.3. |
| 3 | EN | input | Bipolar enable pin: a voltage at or above VEN(HI) (+1.5 V) or at or below VEN(LO) (-1.5 V) enables the output, while a voltage below VDIS(HI) (0.4 V) and above VDIS(LO) (-0.4 V) disables it. |
| 4 | FB | input | Feedback pin for the adjustable version, connected through a resistor divider to OUT to set the output voltage; the feedback pin current IFB is 0.1 µA maximum on the new chip. |
| 5 | OUT | output | Regulator output that requires a capacitor from OUT to GND for stability, with at least 2.2 µF ceramic recommended per section 5.3. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN input voltage range (absolute maximum) | -11 | 0.3 | V | 4 | |||
| EN enable voltage range (absolute maximum) | 5.5 | V | 4 | ||||
| OUT output voltage range (absolute maximum) | -11 | 0.3 | V | 4 | |||
| NR voltage range (old chip) | -11 | 5.5 | V | 4 | |||
| NR voltage range (new chip) | -6 | 0.3 | V | 4 | |||
| Operating junction temperature (absolute maximum) | TJ | -65 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input supply voltage range (recommended) | VIN | -10 | -2.7 | V | 4 | ||
| Output voltage range (recommended) | VOUT | -10 | -1.186 | V | 4 | ||
| Enable voltage range (recommended) | VEN | -10 | 5 | V | 4 | ||
| Output current (recommended) | IOUT | 0 | 200 | mA | 4 | ||
| Input capacitor (old chip) | CIN | 0.1 | 2.2 | µF | 4 | ||
| Input capacitor (new chip) | CIN | 0.47 | µF | 4 | |||
| Output capacitor | COUT | 2.2 | 100 | µF | 4 | ||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 4 | ||
| RθJA junction-to-ambient (new chip) | RθJA | 153.7 | °C/W | 5 | |||
| RθJC(top) junction-to-case top (new chip) | RθJC(top) | 73.4 | °C/W | 5 | |||
| RθJB junction-to-board (new chip) | RθJB | 34.8 | °C/W | 5 | |||
| ΨJT junction-to-top characterization (new chip) | ΨJT | 7.6 | °C/W | 5 | |||
| ΨJB junction-to-board characterization (new chip) | ΨJB | 34.5 | °C/W | 5 | |||
| Output voltage accuracy (old chip) | VO | -1 | 1 | % | TJ = 25°C | 5 | |
| Accuracy fixed and adjustable (old chip) | VO | -2 | 1 | 2 | % | -10V ≤ VI ≤ VO, 0.5V, 10μA ≤ IO ≤ 200mA | 5 |
| Accuracy fixed and adjustable (new chip) | VO | -1.6 | 0.04 | 1.6 | % | -10V ≤ VI ≤ VO, 0.5V, 10μA ≤ IO ≤ 200mA | 5 |
| Line regulation (old chip) | ΔVO(ΔVI) | 0.04 | %/V | -10V ≤ VI ≤ VO(nom), 0.5V | 5 | ||
| Line regulation (new chip) | ΔVO(ΔVI) | -0.003 | %/V | 5 | |||
| Load regulation (old chip) | ΔVO(ΔIO) | 0.002 | %/mA | 0mA ≤ IO ≤ 200mA | 5 | ||
| Load regulation (new chip) | ΔVO(ΔIO) | 0.0001 | %/mA | 5 | |||
| Dropout voltage (old chip) | VDO | 280 | 500 | mV | IO = 200mA, VO = 0.96 × VO(NOM) | 5 | |
| Dropout voltage (new chip) | VDO | 140 | 245 | mV | 5 | ||
| Input UVLO rising (new chip) | VUVLO+ | -2.4 | -2.1 | V | 5 | ||
| Input UVLO falling (new chip) | VUVLO- | -1.9 | -1.4 | V | 5 | ||
| Output current limit (old chip) | ILIM | 300 | 550 | 800 | mA | VO = 0.85 × VO(NOM) | 6 |
| Output current limit (new chip) | ILIM | 300 | 385 | 485 | mA | VO = 0.85 × VO(NOM) | 6 |
| Ground pin current at IO = 0 (old chip) | IGND (IQ) | 130 | 200 | µA | IO = 0mA (IQ), -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Ground pin current at IO = 200mA (old chip) | IGND | 350 | 500 | µA | IO = 200mA, -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Ground pin current at IO = 0 (new chip) | IGND (IQ) | 30 | 55 | µA | IO = 0mA (IQ), -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Ground pin current at IO = 200mA (new chip) | IGND | 290 | 450 | µA | IO = 200mA, -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Shutdown ground pin current (old chip) | ISHDN | 0.1 | 2 | µA | -0.4V ≤ VEN ≤ 0.4V, -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Shutdown ground pin current (new chip) | ISHDN | 0.7 | 2 | µA | -0.4V ≤ VEN ≤ 0.4V, -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Feedback pin current (old chip) | IFB | 0.05 | 1 | µA | -10V ≤ VI ≤ VO, 0.5V | 6 | |
| Feedback pin current (new chip) | IFB | 0.001 | 0.1 | µA | 6 | ||
| EN pin current (old chip) | IEN | 0.1 | 2 | µA | -10V ≤ VI ≤ VO, 0.5V, -10V ≤ VEN ≤ ±3.5V | 6 | |
| EN pin current (new chip) | IEN | 0.6 | 2 | µA | 6 | ||
| Enable threshold positive (old chip) | VEN(HI) | 1.5 | V | 6 | |||
| Enable threshold negative (old chip) | VEN(LO) | -1.5 | V | 6 | |||
| Disable threshold positive (old chip) | VDIS(HI) | 0.4 | V | 6 | |||
| Disable threshold negative (old chip) | VDIS(LO) | -0.4 | V | 6 | |||
| Enable threshold positive (new chip) | VEN(HI) | 1.5 | V | 6 | |||
| Enable threshold negative (new chip) | VEN(LO) | -1.5 | V | 6 | |||
| Disable threshold positive (new chip) | VDIS(HI) | 0.4 | V | 6 | |||
| Disable threshold negative (new chip) | VDIS(LO) | -0.4 | V | 6 | |||
| Thermal shutdown rising (old chip) | Tsd+ | 165 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown reset falling (old chip) | Tsd- | 145 | °C | Reset, temperature decreasing | 6 | ||
| Thermal shutdown rising (new chip) | Tsd+ | 175 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown reset falling (new chip) | Tsd- | 155 | °C | Reset, temperature decreasing | 6 | ||
| Power supply ripple rejection at 1 kHz | PSRR | 65 | dB | IO = 200mA, 1kHz, CI = CO = 10μF | 6 | ||
| Power supply ripple rejection at 10 kHz | PSRR | 48 | dB | IO = 200mA, 10kHz, CI = CO = 10μF | 6 | ||
| Output noise voltage | Vn | 60 | µVRMS | Bandwidth = 10Hz to 100kHz, VO = 2.5V, IO = 200mA, CNR/SS = 0.01µF, CO = 1µF | 6 | ||
| Startup time (old chip) | tSTR | 1 | ms | VO = -2.5V, CO = 1μF, RL = 25Ω | 6 | ||
| Startup time (new chip) | tSTR | 8 | ms | VO = -2.5V, CO = 1μF, RL = 25Ω | 6 |
CAD (KiCad official)
- Symbol:
TPS72301QDBVRQ1 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps72301qdbvrq1-etched.step/tps72301qdbvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps72301qdbvrq1.step/tps72301qdbvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
8ac5df49a742887a, retrieved 2026-11-05, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).