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AD5320BRTZ-500RL7
Public Made by Adomby adom
ANALOG DEVICES INC Global Sourcing Parts, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5320BRTZ-500RL7
ANALOG DEVICES INC · Global Sourcing Parts · SOT-23-6
AD5320BRTZ-500RL7 from ANALOG DEVICES INC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output voltage from the DAC, and the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input; the datasheet states these parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled to GND. |
| 4 | DIN | input | Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 5 | SCLK | input | Serial clock input, with data clocked into the input shift register on the falling edge and transfer rates up to 30 MHz. |
| 6 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC updates after the 16th clock unless SYNC goes high first, which aborts the write as an interrupt. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ANALOG DEVICES INC |
| Package | SOT-23-6 |
| Category | Global Sourcing Parts |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | -16 | 16 | LSB | See Figure 5 | 3 | ||
| Differential Nonlinearity | -1 | 1 | LSB | Guaranteed monotonic by design (see Figure 6) | 3 | ||
| Zero-Code Error | 5 | 40 | mV | All zeroes loaded to DAC register (see Figure 9) | 3 | ||
| Full-Scale Error | -1.25 | -0.15 | % of FSR | All ones loaded to DAC register (see Figure 9) | 3 | ||
| Gain Error | -1.25 | 1.25 | % of FSR | 3 | |||
| Output Voltage Range | VOUT | 0 | V | Upper limit is VDD | 3 | ||
| Output Voltage Settling Time | 8 | 10 | μs | 1/4 scale to 3/4 scale change (400 hex to C00 hex); RL = 2 kΩ, 0 pF < CL < 200 pF (see Figure 19) | 3 | ||
| Output Voltage Settling Time | 12 | μs | RL = 2 kΩ, CL = 500 pF | 3 | |||
| Input Current | -1 | 1 | μA | 3 | |||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V | 3 | ||
| Input Low Voltage | VINL | 0.6 | V | VDD = 3 V | 3 | ||
| Input High Voltage | VINH | 2.4 | V | VDD = 5 V | 3 | ||
| Input High Voltage | VINH | 2.1 | V | VDD = 3 V | 3 | ||
| Supply Voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Supply Current (Normal Mode) | IDD | 140 | 250 | μA | DAC active and excluding load current; VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 3 | |
| Supply Current (Normal Mode) | IDD | 115 | 200 | μA | DAC active and excluding load current; VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 3 | |
| Supply Current (All Power-Down Modes) | IDD | 0.2 | 1 | μA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 3 | |
| Supply Current (All Power-Down Modes) | IDD | 0.05 | 1 | μA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND | 3 | |
| SCLK cycle time | t1 | 50 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| SCLK cycle time | t1 | 33 | ns | VDD = 3.6 V to 5.5 V | 4 | ||
| SCLK high time | t2 | 13 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| SCLK low time | t3 | 22.5 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| SCLK low time | t3 | 13 | ns | VDD = 3.6 V to 5.5 V | 4 | ||
| SYNC to SCLK rising edge setup time | t4 | 0 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| Data setup time | t5 | 5 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| Data hold time | t6 | 4.5 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| SCLK falling edge to SYNC rising edge | t7 | 0 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| Minimum SYNC high time | t8 | 50 | ns | VDD = 2.7 V to 3.6 V | 4 | ||
| Minimum SYNC high time | t8 | 33 | ns | VDD = 3.6 V to 5.5 V | 4 | ||
| Maximum SCLK frequency | 20 | MHz | VDD = 2.7 V to 3.6 V | 4 | |||
| Maximum SCLK frequency | 30 | MHz | VDD = 3.6 V to 5.5 V | 4 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 5 | ||
| Digital Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V | 5 | |||
| VOUT to GND | VOUT | -0.3 | V | Upper limit VDD + 0.3 V | 5 | ||
| Operating Temperature Range (Industrial, B Version) | -40 | 105 | °C | Industrial (B Version) | 5 | ||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Junction Temperature | TJ | 150 | °C | TJ Max | 5 | ||
| Lead Temperature, Soldering | 215 | °C | Vapor phase (60 sec) | 5 | |||
| Lead Temperature, Soldering | 220 | °C | Infrared (15 sec) | 5 | |||
| Zero-Code Error Drift | -20 | μV/°C | 3 | ||||
| Gain Temperature Coefficient | -5 | ppm of FSR/°C | 3 | ||||
| Slew Rate | 1 | V/μs | 3 | ||||
| Capacitive Load Stability | 470 | pF | RL = ∞ | 3 | |||
| Capacitive Load Stability | 1000 | pF | RL = 2 kΩ | 3 | |||
| Digital-to-Analog Glitch Impulse | 20 | nV-s | 1 LSB change around major carry (see Figure 22) | 3 | |||
| Digital Feedthrough | 0.5 | nV-s | 3 | ||||
| DC Output Impedance | 1 | Ω | 3 | ||||
| Short Circuit Current | 50 | mA | VDD = 5 V | 3 | |||
| Short Circuit Current | 20 | mA | VDD = 3 V | 3 | |||
| Power-Up Time | 2.5 | μs | Coming out of power-down mode, VDD = 5 V | 3 | |||
| Power-Up Time | 5 | μs | Coming out of power-down mode, VDD = 3 V | 3 | |||
| Pin Capacitance | 3 | pF | 3 | ||||
| Power Efficiency | IOUT/IDD | 93 | % | ILOAD = 2 mA, VDD = 5 V | 3 | ||
| Thermal Impedance, Junction to Ambient (SOT-23) | θJA | 240 | °C/W | SOT-23 package | 5 |
CAD (KiCad official)
- Symbol:
AD5320BRTZ-500RL7 - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
ad5320brtz-500rl7-etched.step/ad5320brtz-500rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5320brtz-500rl7.step/ad5320brtz-500rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ANALOG DEVICES INC datasheet (20 pp, sha256
e9eeb79262f1e035, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).