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HX65HVD255-S

Public Made by Adom

by adom

ZHHXDZ CAN Transceivers, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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HX65HVD255-S

ZHHXDZ · CAN Transceivers · SOP-8

HX65HVD255-S from ZHHXDZ, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input; if TXD is held low longer than the dominant time-out tdom (300 to 700 µs), the transmitter is disabled and the bus is released to recessive.
2 GND power_in Ground supply pin for the transceiver.
3 VCC power_in Supply voltage of 5 V ±10% (4.5 V to 5.5 V operating range).
4 RXD output Receive data output that reads the CAN bus state; it is high in the recessive state and low in the dominant state.
5 NC unconnected Common-mode stabilization output with a stabilised output voltage of 0.3VCC to 0.7VCC for -500 µA < Io < 500 µA.
6 CANL bidirectional LOW-level CAN bus line; bus-side port rated -60 V to +60 V with transient voltage ±200 V.
7 CANH bidirectional HIGH-level CAN bus line; bus-side port rated -60 V to +60 V with transient voltage ±200 V.
8 S input High-speed and standby mode selection: grounding S selects high-speed mode, while high or unconnected S selects standby mode.

Key specifications

Parameter Value
Manufacturer ZHHXDZ
Package SOP-8
Category Communication Interface Chip
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -4.5 5.5 V 2
MCU side port voltage (TXD, RXD, S) -0.3 V max printed as VCC+0.3 2
Bus-side port voltage (CANL, CANH, NC) -60 60 V 2
Transient voltage pin 6, 7 Vtr -200 200 V Pin 6, 7 2
Storage temperature -55 150 ℃ 2
Ambient temperature -40 85 ℃ 2
Welding temperature range 300 ℃ 2
SOP8 continuous power consumption 400 mW 2
CANH output voltage (dominant) VOH(D) 2.9 3.4 4.5 V VI=0V, S=0V, RL=60Ω, F1、2 2
CANL output voltage (dominant) VOL(D) 0.8 1.5 V 2
Bus output differential voltage (implicit) VO(R) 2 2.5 3 V VI=3V, S=0V, RL=60Ω, F1、2 2
Bus output differential voltage (dominant) VOD(D) 1.5 3 V VI=0V, S=0V, RL=60Ω, F1、2 2
Bus output differential voltage (implicit) VOD(R) -0.012 0.012 V VI=3V, S=0V, F1、2 2
Bus output differential voltage (implicit), no load VOD(R) -0.5 0.05 V VI=3V, S=0V, NO LOAD 2
Dominant output voltage symmetry Vdom(TX)sym -400 400 mV 2
Common mode output voltage VOC 2 2.5 3 V S=0V, F8 2
Explicit and implicit common mode output voltage difference ΔVOC 30 mV 2
Short-circuit output current IOS -105 -72 mA CANH=-12V, CANL=open, F11 2
Short-circuit output current IOS 0.36 1 mA CANH=12V, CANL=open, F11 2
Short-circuit output current IOS -1 0.5 mA CANL=-12V, CANH=open, F11 2
Short-circuit output current IOS 71 105 mA CANL=12V, CANH=open, F11 2
Hidden output current IO(R) -2 2.5 mA -27V<CANH<32V, 0<VCC<5.25V 2
Transmission delay (low to high) tPLH 25 65 120 ns S=0V, F4 2
Transmission delay (high to low) tPHL 25 45 90 ns 2
Explicit timeout tdom 300 450 700 μs F10 2
Bus wake-up time tBUS 0.7 5 μs 2
Positive input threshold VIT+ 800 900 mV S=0V, F5 3
Negative input threshold VIT- 500 650 mV 3
Comparator threshold hysteresis interval VHYS 100 125 mV 3
High level output voltage VOH 4 4.6 V IO=-2mA, F6 3
Low level output voltage VOL 0.2 0.4 V IO=2mA, F6 3
CANH, CANL input resistance RIN 15 30 40 KΩ TXD=3V, S=0V 3
CANH, CANL differential input resistors RID 30 80 KΩ 3
RI(CANH), RIN(CANL) mismatches RImatch -3 3 % CANH=CANL 3
Common mode voltage range VCOM -12 12 V 3
Propagation delay (low to high) tPLH 60 100 130 ns S=0V or VCC, F6 3
Propagation delay (high to low) tPHL 45 70 90 ns 3
Loop delay 1, driver input to receiver output, implicit to explicit Td(LOOP1) 90 190 ns S=0V, F9 3
Loop delay 2, driver input to receiver output, explicit to implicit Td(LOOP2) 90 190 ns 3
Over temperature shutdown Tj(sd) 155 165 180 ℃ 3
Leakage current (TXD stabilised output) IO(S) -5 5 μA S=2V, -12V<VO<12V 3
TXD port high level input current IIH(TXD) -2 2 μA VI=VCC 3
TXD port low level input current IIL(TXD) -50 -10 μA VI=0 3
Input high level lower limit VIH 2 V max printed as VCC+0.3 3
Input low level limit VIL -0.3 0.8 V 3
Silent mode power consumption ICC 5 12 μA S=VCC, VI=VCC 3
Dominant power consumption ICC 50 70 mA VI=0V, S=0V, LOAD=60Ω 3
Implicit power consumption ICC 6 10 mA VI=VCC, S=0V, NO LOAD 3

CAD (KiCad official)

  • Symbol: HX65HVD255-S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: hx65hvd255-s-etched.step / hx65hvd255-s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hx65hvd255-s.step / hx65hvd255-s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ZHHXDZ datasheet (8 pp, sha256 23294b6156daf654, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF