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MSP430F2272TRHAR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F2272TRHAR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)
MSP430F2272TRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVSS | power_in | Digital ground reference. |
| 2 | XOUT/P2.7 | bidirectional | Output terminal of the crystal oscillator, also general-purpose digital I/O P2.7; if used as an input, excess current flows until P2SEL.7 is cleared. |
| 3 | XIN/P2.6 | bidirectional | Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6. |
| 4 | DVSS | power_in | Digital ground reference. |
| 5 | RST/NMI/SBWTDIO | input | Reset or nonmaskable interrupt input; also Spy-Bi-Wire test data input/output during programming and test. |
| 6 | P2.0/ACLK/A0 | bidirectional | General-purpose digital I/O; alternately ACLK output or ADC10 analog input A0. |
| 7 | P2.1/TAINCLK/SMCLK/A1 | bidirectional | General-purpose digital I/O; alternately Timer_A INCLK clock input, SMCLK output, or ADC10 analog input A1. |
| 8 | P2.2/TA0/A2 | bidirectional | General-purpose digital I/O; alternately Timer_A CCI0B capture input / BSL receive, Timer_A TA0 compare output, or ADC10 analog input A2. |
| 9 | P3.0/UCB0STE/UCA0CLK/A5 | bidirectional | General-purpose digital I/O; alternately USCI_B0 slave transmit enable, USCI_A0 clock input/output, or ADC10 analog input A5. |
| 10 | P3.1/UCB0SIMO/UCB0SDA | bidirectional | General-purpose digital I/O; alternately USCI_B0 SPI slave-in/master-out or I2C data (SDA). |
| 11 | P3.2/UCB0SOMI/UCB0SCL | bidirectional | General-purpose digital I/O; alternately USCI_B0 SPI slave-out/master-in or I2C clock (SCL). |
| 12 | P3.3/UCB0CLK/UCA0STE | bidirectional | General-purpose digital I/O; alternately USCI_B0 clock input/output or USCI_A0 slave transmit enable. |
| 13 | AVSS | power_in | Analog ground reference. |
| 14 | AVCC | power_in | Analog supply voltage. |
| 15 | P4.0/TB0 | bidirectional | General-purpose digital I/O; alternately Timer_B capture input CCI0A or compare output OUT0. |
| 16 | P4.1/TB1 | bidirectional | General-purpose digital I/O; alternately Timer_B capture input CCI1A or compare output OUT1. |
| 17 | P4.2/TB2 | bidirectional | General-purpose digital I/O; alternately Timer_B capture input CCI2A or compare output OUT2. |
| 18 | P4.3/TB0/A12 | bidirectional | General-purpose digital I/O; alternately Timer_B capture input CCI0B / compare output OUT0 or ADC10 analog input A12. |
| 19 | P4.4/TB1/A13 | bidirectional | General-purpose digital I/O; alternately Timer_B capture input CCI1B / compare output OUT1 or ADC10 analog input A13. |
| 20 | P4.5/TB2/A14 | bidirectional | General-purpose digital I/O; alternately Timer_B compare output OUT2 or ADC10 analog input A14. |
| 21 | P4.6/TBOUTH/A15 | bidirectional | General-purpose digital I/O; alternately Timer_B switch-all-TB0-to-TB3-outputs-to-high-impedance input or ADC10 analog input A15. |
| 22 | P4.7/TBCLK | bidirectional | General-purpose digital I/O; alternately Timer_B clock signal TBCLK input. |
| 23 | P3.4/UCA0TXD/UCA0SIMO | bidirectional | General-purpose digital I/O; alternately USCI_A0 UART transmit data output or SPI slave-in/master-out. |
| 24 | P3.5/UCA0RXD/UCA0SOMI | bidirectional | General-purpose digital I/O; alternately USCI_A0 UART receive data input or SPI slave-out/master-in. |
| 25 | P3.6/A6 | bidirectional | General-purpose digital I/O; alternately ADC10 analog input A6. |
| 26 | P3.7/A7 | bidirectional | General-purpose digital I/O; alternately ADC10 analog input A7. |
| 27 | P2.3/TA1/A3/VREF-/VeREF- | bidirectional | General-purpose digital I/O; alternately Timer_A CCI1B capture input / TA1 compare output, ADC10 analog input A3, or negative reference voltage input. |
| 28 | P2.4/TA2/A4/VREF+/VeREF+ | bidirectional | General-purpose digital I/O; alternately Timer_A TA2 compare output, ADC10 analog input A4, or positive reference voltage output or input. |
| 29 | P1.0/TACLK/ADC10CLK | bidirectional | General-purpose digital I/O; alternately Timer_A clock signal TACLK input or ADC10 conversion clock. |
| 30 | P1.1/TA0 | bidirectional | General-purpose digital I/O; alternately Timer_A capture input CCI0A or compare output OUT0, and BSL transmit. |
| 31 | P1.2/TA1 | bidirectional | General-purpose digital I/O; alternately Timer_A capture input CCI1A or compare output OUT1. |
| 32 | P1.3/TA2 | bidirectional | General-purpose digital I/O; alternately Timer_A capture input CCI2A or compare output OUT2. |
| 33 | P1.4/SMCLK/TCK | bidirectional | General-purpose digital I/O; alternately SMCLK signal output or JTAG test clock input for device programming and test. |
| 34 | P1.5/TA0/TMS | bidirectional | General-purpose digital I/O; alternately Timer_A compare output OUT0 or JTAG test mode select input for device programming and test. |
| 35 | P1.6/TA1/TDI/TCLK | bidirectional | General-purpose digital I/O; alternately Timer_A compare output OUT1 or JTAG test data input / test clock input for programming and test. |
| 36 | P1.7/TA2/TDO/TDI | bidirectional | General-purpose digital I/O; alternately Timer_A compare output OUT2 or JTAG test data output / test data input (selected via JTAG instruction) for programming and test. |
| 37 | TEST/SBWTCK | input | Selects test mode for JTAG pins on Port 1 and is the Spy-Bi-Wire test clock input during programming and test; the device protection fuse is connected to this pin. |
| 38 | DVCC | power_in | Digital supply voltage (device rated 1.8 V to 3.6 V per the feature list). |
| 39 | DVCC | power_in | Digital supply voltage (device rated 1.8 V to 3.6 V per the feature list). |
| 40 | P2.5/ROSC | bidirectional | General-purpose digital I/O; alternately input for an external DCO resistor that defines the DCO frequency. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
MSP430F2272TRHAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
msp430f2272trhar-etched.step/msp430f2272trhar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f2272trhar.step/msp430f2272trhar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (105 pp, sha256
1c1e00a7c54bebc8, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).