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Contents

README

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SWD7N65D

Samwin · MOSFETs · TO-252

SWD7N65D from Samwin, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate control input of the N-channel MOSFET, with a maximum gate-to-source voltage of ±30 V and a typical total gate charge of 30 nC.
2 D passive Drain terminal, rated for 650 V drain-to-source voltage and 7 A continuous drain current (28 A pulsed).
3 S passive Source terminal, with continuous body-diode source current rated at 7 A and pulsed source current of 28 A.

Key specifications

Parameter Value
Manufacturer Samwin
Package TO-252
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain to source voltage VDSS 650 V 1
Continuous drain current ID 7 A @TC=25oC; limited by junction temperature 1
Continuous drain current ID 4.4 A @TC=100oC; limited by junction temperature 1
Drain current pulsed IDM 28 A note 1 1
Gate to source voltage VGS -30 30 V 1
Single pulsed avalanche energy EAS 430 mJ note 2 1
Repetitive avalanche energy EAR 40 mJ note 1 1
Peak diode recovery dv/dt dv/dt 5 V/ns note 3 1
Operating junction & storage temperature TSTG, TJ -55 150 oC 1
Maximum lead temperature for soldering TL 300 oC 1/8 from case for 5 seconds 1
Drain to source breakdown voltage BVDSS 650 V VGS=0V, ID=250uA 2
Drain to source leakage current IDSS 1 uA VDS=650V, VGS=0V 2
Drain to source leakage current IDSS 50 uA VDS=520V, TJ=125oC 2
Gate to source leakage current, forward IGSS 100 nA VGS=30V, VDS=0V 2
Gate to source leakage current, reverse IGSS -100 nA VGS=-30V, VDS=0V 2
Gate threshold voltage VGS(TH) 2.5 4.5 V VDS=VGS, ID=250uA 2
Drain to source on state resistance RDS(ON) 1.1 1.4 Ω VGS=10V, ID = 3.5A, TJ=25oC 2
Drain to source on state resistance RDS(ON) 2.4 Ω VGS=10V, ID = 3.5A, TJ=125oC 2
Continuous source current IS 7 A Integral reverse p-n Junction diode in the MOSFET 2
Pulsed source current ISM 28 A 2
Diode forward voltage drop VSD 1.4 V IS=7A, VGS=0V 2
Breakdown voltage temperature coefficient ΔBVDSS/ΔTJ 0.51 V/oC ID=250uA, referenced to 25oC 2
Forward transconductance Gfs 6.3 S VDS=30 V, ID =3.5A 2
Input capacitance Ciss 1230 pF VGS=0V, VDS=25V, f=1MHz 2
Output capacitance Coss 108 pF VGS=0V, VDS=25V, f=1MHz 2
Reverse transfer capacitance Crss 16 pF VGS=0V, VDS=25V, f=1MHz 2
Turn on delay time td(on) 16 ns VDS=350V, ID=7A, RG=25Ω (note 4,5) 2
Rising time tr 36 ns VDS=350V, ID=7A, RG=25Ω (note 4,5) 2
Turn off delay time td(off) 83 ns VDS=350V, ID=7A, RG=25Ω (note 4,5) 2
Fall time tf 40 ns VDS=350V, ID=7A, RG=25Ω (note 4,5) 2
Total gate charge Qg 30 nC VDS=520V, VGS=10V, ID=7A (note 4,5) 2
Gate-source charge Qgs 5 nC VDS=520V, VGS=10V, ID=7A (note 4,5) 2
Gate-drain charge Qgd 15 nC VDS=520V, VGS=10V, ID=7A (note 4,5) 2
Gate resistance Rg 1.7 Ω VDS=0V, Scan F mode 2
Reverse recovery time trr 436 ns IS=7A, VGS=0V, dIF/dt=100A/us 2
Reverse recovery charge Qrr 3.6 uC IS=7A, VGS=0V, dIF/dt=100A/us 2

CAD (KiCad official)

  • Symbol: SWD7N65D
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: swd7n65d-etched.step / swd7n65d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); swd7n65d.step / swd7n65d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Samwin datasheet (8 pp, sha256 32b0f76f8e0c9f45, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF