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WM8231GEFL

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Cirrus Logic Analog Front End (AFEs), QFN-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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WM8231GEFL

Cirrus Logic · Analog Front End (AFEs) · QFN-56(8x8)

WM8231GEFL from Cirrus Logic, in a QFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF2C output Mid reference voltage output that must be connected to AGND via a decoupling capacitor.
2 VRLC/VBIAS bidirectional Reference voltage input/output for the reset level clamp and bias.
3 VREF3C output Lower reference voltage output that must be connected to AGND via a decoupling capacitor.
4 VREF1C output Upper reference voltage output that must be connected to AGND via a decoupling capacitor.
5 SEN input Enables the serial interface when high.
6 SDO output Serial interface data output.
7 SCK input Serial interface clock input.
8 SDI input Serial interface data input.
9 LDO2VDD power_in Analogue supply input for LDO2, 2.97 V to 3.63 V (3.3 V typical).
10 LDO2GND power_in Analogue ground for LDO2, intended to be at the same potential as AGND and DBGND.
11 LDO2VOUT power_out LDO2 output that must be connected to AGND via a decoupling capacitor.
12 DSLCT2 input Device select 2 input.
13 MCLK input Master clock input, 5 to 35 MHz.
14 DSLCT1 input Device select 1 input.
15 D5N/OP[9] output LVDS data output 5 negative, or CMOS output 9.
16 D5P/OP[8] output LVDS data output 5 positive, or CMOS output 8.
17 D4N/OP[7] output LVDS data output 4 negative, or CMOS output 7.
18 D4P/OP[6] output LVDS data output 4 positive, or CMOS output 6.
19 DCLKN/OC[2] output LVDS clock output negative, or CMOS flag output.
20 DCLKP/OC[1] output LVDS clock output positive, or CMOS clock output.
21 DBGND power_in Digital ground, intended to be at the same potential as AGND and LDOGND, as differential voltages degrade performance.
22 DBVDD power_in Supply input, 2.97 V to 3.63 V (3.3 V typical).
23 D3N/OP[5] output LVDS data output 3 negative, or CMOS output 5.
24 D3P/OP[4] output LVDS data output 3 positive, or CMOS output 4.
25 D2N/OP[3] output LVDS data output 2 negative, or CMOS output 3.
26 D2P/OP[2] output LVDS data output 2 positive, or CMOS output 2.
27 D1N/OP[1] output LVDS data output 1 negative, or CMOS output 1.
28 D1P/OP[0] output LVDS data output 1 positive, or CMOS output 0.
29 HZCTRL input Internal use only; must be connected to AGND.
30 MON output Clock monitor output.
31 LDO1VOUT power_out LDO1 output that must be connected to AGND via a decoupling capacitor.
32 LDO1GND power_in Analogue ground for LDO1, intended to be at the same potential as AGND and DBGND.
33 LDO1VDD power_in Analogue supply input for LDO1, 2.97 V to 3.63 V (3.3 V typical).
34 TGSYNC bidirectional Sensor timing sync pulse input/output.
35 CLK1 output Sensor timing output 1.
36 CLK2 output Sensor timing output 2.
37 CLK3 output Sensor timing output 3.
38 CLK4 output Sensor timing output 4.
39 CLK5 output Sensor timing output 5.
40 CLK6 output Sensor timing output 6.
41 CLK7 output Sensor timing output 7.
42 CLK8 output Sensor timing output 8.
43 CLK9 output Sensor timing output 9.
44 CLK10 output Sensor timing output 10.
45 CLK11 output Sensor timing output 11.
46 AGND3 power_in Analogue ground.
47 NC unconnected Not connected internally.
48 IN2 input Analogue input 2.
49 AGND2 power_in Analogue ground.
50 AVDD2 power_in Analogue supply input, 2.97 V to 3.63 V (3.3 V typical).
51 NC unconnected Not connected internally.
52 INP4 input Analogue input 4.
53 NC unconnected Not connected internally.
54 INP6 input Analogue input 6.
55 AVDD1 power_in Analogue supply input, 2.97 V to 3.63 V (3.3 V typical).
56 AGND1 power_in Analogue ground.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package QFN-56(8x8)
Category ADC/DAC/Data Conversion
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature range TA -40 85 C 7
Analogue supply voltage AVDD1-2 2.97 3.3 3.63 V AVDD1-2, LDO1VDD-LDO2VDD, DBVDD 7
Analogue supply voltage AVDD1-2 -0.3 5 V relative to GND (GND-0.3V to GND+5V) 7
Analogue grounds AGND1-3 -0.3 0.3 V relative to GND (GND-0.3V to GND+0.3V) 7
Analogue inputs (IN1-6) IN1-6 -0.3 V max AVDD+0.3V 7
Other analogue pins -0.3 V max AVDD+0.3V 7
Digital I/O pins -0.3 V max AVDD+0.3V 7
Operating temperature range TA -40 85 C 7
Storage temperature after soldering -65 150 C 7
Conversion rate per channel 5 35 MSPS 8
Integral non-linearity (pk-pk/2) INL -4 4 LSB 10-bit 8
Differential non-linearity DNL -1.5 1.5 LSB 10-bit 8
Max gain, each channel (Ga) Ga MAX 8 9.9 11.43 V/V AGAIN[4:0] = 1F(hex) 8
Min gain, each channel (Ga) Ga MIN 0.44 0.6 0.77 V/V AGAIN[4:0] = 0(hex) 8
Offset DAC output voltage -400 -250 -100 mV Code 00(hex) 9
Offset DAC output voltage 100 250 400 mV Code FF(hex) 9
Input return bias voltage VREF2C 1.14 1.2 1.26 V 9
Diff. Reference voltage (VREF1C-VREF3C) VREF1C3C 0.72 0.8 0.88 V ADCFS=0 9
Diff. Reference voltage (VREF1C-VREF3C) VREF1C3C 1 1.2 1.35 V ADCFS=1 9
VRLC input voltage range VRLC 0.11 3 V SF_INP=0 9
VRLC input voltage range VRLC 0.11 1.2 V SF_INP=1 9
High level input voltage VIH 0.7 V 0.7 x AVDD 9
Low level input voltage VIL 0.2 V 0.2 x AVDD 9
High level input current IIH 1 uA 9
Low level input current IIL 1 uA 9
Data output skew tSKOP -500 500 ps MCLK=30MHz 16
LVDS output skew tSKLV -250 250 ps MCLK=35MHz 16
LVDS output signal rise time tLVTr 1 ns MCLK=35MHz 16
LVDS output signal fall time tLVTf 1 ns MCLK=35MHz 16

CAD (KiCad official)

  • Symbol: WM8231GEFL
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56(8x8) (KiCad packages3D, STEP)
  • 3D model files: wm8231gefl-etched.step / wm8231gefl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); wm8231gefl.step / wm8231gefl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (143 pp, sha256 c1ba6969e1e6c89a, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF