AD7367BRUZ-5500RL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DOUTA	tri_state	Serial Data Output for ADC A. 14-bit conversion data (AD7367-5) is clocked out MSB-first on the falling edge of SCLK; 14 SCLK cycles are required per conversion. Tri-state when CS is high.
2	VDRIVE	power_in	Logic interface supply, 2.7 V to 5.25 V. Sets the operating voltage of the digital interface independent of AVCC/DVCC (must not differ from them by more than 0.3 V during operation of the digital pins). Decouple to DGND.
3	DVCC	power_in	Digital supply voltage, 4.75 V to 5.25 V. Should be at the same potential as AVCC (≤0.3 V difference, tie together for best performance). Decouple to DGND with 10 µF and 100 nF.
4	RANGE1	input	Analog input range selection logic input (MSB of range code). Combined with RANGE0, selects ±10 V, ±5 V, or 0 V to +10 V input range. See Table 8 for coding.
5	RANGE0	input	Analog input range selection logic input (LSB of range code). Combined with RANGE1, selects the bipolar/unipolar input range for both ADCs.
6	ADDR	input	Multiplexer select logic input. Selects the pair of channels to be simultaneously converted: low = channel 1 on both ADC A and ADC B (VA1/VB1); high = channel 2 (VA2/VB2). Latched on the rising edge of BUSY.
7	AGND	power_in	Analog ground. Reference for all analog circuitry. Both AGND pins (7 and 17) must be tied to the AGND plane and must be within 0.3 V of DGND (including transients).
8	AVCC	power_in	Analog supply voltage for the ADC cores, 4.75 V to 5.25 V. Should share potential with DVCC (tie together for best performance). Decouple to AGND with 10 µF and 100 nF.
9	DCAPA	passive	Decoupling capacitor pin for ADC A reference buffer. Connect a 680 nF decoupling capacitor to AGND. When an external reference is used (REFSEL = 0), the reference is applied to this pin; internal reference can also be tapped here.
10	VSS	power_in	Negative supply for the high-voltage analog input structure. Must be ≤ −5 V (typically −16.5 V to −5 V; −12 V minimum required for ±12 V input range). Decouple with 10 µF and 100 nF to AGND.
11	VA1	input	Single-ended analog input, ADC A channel 1. Input range programmable via RANGE0/RANGE1 (±10 V, ±5 V, or 0 V to +10 V; ±12 V with external 3 V reference).
12	VA2	input	Single-ended analog input, ADC A channel 2. Input range programmable via RANGE0/RANGE1.
13	VB2	input	Single-ended analog input, ADC B channel 2. Input range programmable via RANGE0/RANGE1.
14	VB1	input	Single-ended analog input, ADC B channel 1. Input range programmable via RANGE0/RANGE1.
15	VDD	power_in	Positive supply for the high-voltage analog input structure. Must be ≥ +5 V (typically +5 V to +16.5 V; +12 V minimum required for ±12 V input range). Decouple with 10 µF and 100 nF to AGND.
16	DCAPB	passive	Decoupling capacitor pin for ADC B reference buffer. Connect a 680 nF decoupling capacitor to AGND. Used as external reference input for ADC B when REFSEL = 0.
17	AGND	power_in	Analog ground. Reference for all analog circuitry. Both AGND pins (7 and 17) must be tied to the AGND plane and must be within 0.3 V of DGND.
18	REFSEL	input	Internal/External reference selection logic input. High = on-chip 2.5 V reference used (DCAPA/DCAPB tied to decoupling caps only). Low = external reference supplied via DCAPA and/or DCAPB.
19	CS	input	Chip Select, active-low logic input. Frames the serial data transfer; when CS is low, the output bus is enabled and conversion results are clocked out on DOUTA and DOUTB.
20	SCLK	input	Serial clock logic input. Provides the clock for reading conversion data on DOUTA/DOUTB. Maximum fSCLK = 20 MHz.
21	CNVST	input	Conversion Start, edge-triggered logic input. Falling edge places the track/hold in hold mode and initiates a conversion. If held low at end of conversion, the part enters power-down; rising edge instructs it to power up again.
22	BUSY	output	Busy output. Transitions high when a conversion starts and remains high until the conversion completes. Rising edge latches the ADDR/RANGE inputs for the next conversion.
23	DOUTB	tri_state	Serial Data Output for ADC B. 14-bit conversion data clocked out MSB-first on falling edges of SCLK. Tri-state when CS is high.
24	DGND	power_in	Digital ground. Reference for all digital circuitry. Must connect to DGND plane and must be within 0.3 V of AGND (including transients).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-24
Category	Data Acquisition
Pins	24

Ordering variants

Same part, different packaging or reel option.

AD7367BRUZ-5500RL7
AD7367BRUZ-5-RL7

CAD (KiCad official)

Symbol: AD7367BRUZ-5500RL7
Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
3D model: TSSOP-24 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 18fe044dea8fd51d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF