component
TPS65263QRHBTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65263QRHBTQ1
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65263QRHBTQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN3 | input | Enable for buck3; float to enable, and a resistor divider on this pin can set the buck3 input UVLO. |
| 2 | SDA | bidirectional | I2C interface data pin; float or connect to GND to disable I2C communication. |
| 3 | SCL | input | I2C interface clock pin; float or connect to GND to disable I2C communication. |
| 4 | AGND | power_in | Analog ground common to the buck controllers and other analog circuits, which must be routed separately from high-current power grounds to the (-) terminal of the VIN bypass capacitor. |
| 5 | VOUT2 | input | Buck2 output voltage sense pin. |
| 6 | FB2 | input | Feedback Kelvin sensing pin for buck2 output voltage; connect to the buck2 resistor divider. |
| 7 | COMP2 | passive | Error amplifier output and loop compensation pin for buck2; connect a series resistor and capacitor to compensate peak current PWM mode. |
| 8 | SS2 | passive | Soft-start and tracking input for buck2 with an internal 5.2-µA pullup; soft-start time is set by a capacitor to ground. |
| 9 | BST2 | passive | Boot-strapped supply to the buck2 high-side floating gate driver; connect a capacitor (recommended 47 nF) from BST2 to LX2. |
| 10 | LX2 | output | Buck2 switching node connected to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN2 voltage. |
| 11 | PGND2 | power_in | Buck2 power ground; connect as close as practical to the (-) terminal of the VIN2 input ceramic capacitor. |
| 12 | PVIN2 | power_in | Buck2 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF). |
| 13 | PVIN3 | power_in | Buck3 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF). |
| 14 | PGND3 | power_in | Buck3 power ground; connect as close as practical to the (-) terminal of the VIN3 input ceramic capacitor. |
| 15 | LX3 | output | Buck3 switching node connected to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN3 voltage. |
| 16 | BST3 | passive | Boot-strapped supply to the buck3 high-side floating gate driver; connect a capacitor (recommended 47 nF) from BST3 to LX3. |
| 17 | SS3 | passive | Soft-start and tracking input for buck3 with an internal 5.2-µA pullup; soft-start time is set by a capacitor to ground. |
| 18 | COMP3 | passive | Error amplifier output and loop compensation pin for buck3; connect a series resistor and capacitor to compensate peak current PWM mode. |
| 19 | FB3 | input | Feedback Kelvin sensing pin for buck3 output voltage; connect to the buck3 resistor divider. |
| 20 | PGOOD | output | Output voltage supervision pin; asserted high when all bucks are within the PGOOD monitor regulation range. |
| 21 | ROSC | input | Clock frequency adjustment pin; a resistor to ground sets the switching frequency, and an external clock applied here synchronizes the internal oscillator. |
| 22 | FB1 | input | Feedback Kelvin sensing pin for buck1 output voltage; connect to the buck1 resistor divider. |
| 23 | COMP1 | passive | Error amplifier output and loop compensation pin for buck1; connect a series resistor and capacitor to compensate peak current PWM mode. |
| 24 | SS1 | passive | Soft-start and tracking input for buck1 with an internal 5.2-µA pullup; soft-start time is set by a capacitor to ground. |
| 25 | BST1 | passive | Boot-strapped supply to the buck1 high-side floating gate driver; connect a capacitor (recommended 47 nF) from BST1 to LX1. |
| 26 | LX1 | output | Buck1 switching node connected to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN1 voltage. |
| 27 | PGND1 | power_in | Buck1 power ground; connect as close as practical to the (-) terminal of the VIN1 input ceramic capacitor. |
| 28 | PVIN1 | power_in | Buck1 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF). |
| 29 | VIN | power_in | Buck controller power supply input. |
| 30 | V7V | power_out | Internal LDO output for the gate driver and internal controller; connect a 10-µF ceramic capacitor from this pin to power ground. |
| 31 | EN1 | input | Enable for buck1; float to enable, and a resistor divider on this pin can set the buck1 input UVLO. |
| 32 | EN2 | input | Enable for buck2; float to enable, and a resistor divider on this pin can set the buck2 input UVLO. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum: PVIN1, PVIN2, PVIN3, VIN | -0.3 | 20 | V | 5 | |||
| Absolute maximum: LX1, LX2, LX3 | -1 | 20 | V | Maximum withstand voltage transient < 20 ns | 5 | ||
| Absolute maximum: BST1, BST2, BST3 | -0.3 | 7 | V | Referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| Absolute maximum: EN1, EN2, EN3, V7V, VOUT2, SCL, SDA, PGOOD | -0.3 | 7 | V | 5 | |||
| Absolute maximum: FB1, FB2, FB3, COMP1, COMP2, COMP3, ROSC, SS1, SS2, SS3 | -0.3 | 3.6 | V | 5 | |||
| Absolute maximum: AGND, PGND1, PGND2, PGND3 | -0.3 | 0.3 | V | 5 | |||
| Absolute maximum: operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Absolute maximum: storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Recommended operating: PVIN1, PVIN2, PVIN3, VIN | 4 | 18 | V | 5 | |||
| Recommended operating: LX1, LX2, LX3 | -0.8 | 18 | V | Maximum withstand voltage transient <20 ns | 5 | ||
| Recommended operating: BST1, BST2, BST3 | -0.1 | 6.8 | V | Referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| Recommended operating: EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA | -0.1 | 6.3 | V | 5 | |||
| Recommended operating: FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3 | -0.1 | 3 | V | 5 | |||
| Recommended operating: operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Input voltage range | VIN | 4 | 18 | V | 6 | ||
| VIN UVLO rising threshold | 3.5 | 3.8 | 4 | V | VIN rising | 6 | |
| VIN UVLO falling threshold | 3.1 | 3.3 | 3.5 | V | VIN falling | 6 | |
| Shutdown supply current | IDDSDN | 4 | 9.5 | 18 | µA | EN1 = EN2 = EN3 = 0 V | 6 |
| Input quiescent current without buck switching | IDDQ_NSW | 550 | 780 | 1150 | µA | EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V | 6 |
| Input quiescent current without buck1 switching (buck1 enabled) | IDDQ_NSW1 | 180 | 370 | 590 | µA | EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V | 6 |
| Input quiescent current without buck2 switching (buck2 enabled) | IDDQ_NSW2 | 180 | 370 | 590 | µA | EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8V | 6 |
| Input quiescent current without buck3 switching (buck3 enabled) | IDDQ_NSW3 | 180 | 370 | 590 | µA | EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V | 6 |
| V7V LDO current limit | IOCP_V7V | 78 | 185 | 260 | mA | 6 | |
| Feedback voltage | VFB | 0.594 | 0.6 | 0.606 | V | VCOMP = 1.2 V | 6 |
| EN1/2/3 high-level input voltage | VENXH | 1.12 | 1.2 | 1.26 | V | 6 | |
| EN1/2/3 low-level input voltage | VENXL | 1.05 | 1.15 | 1.21 | V | 6 | |
| EN1/2/3 pullup current | IENX1 | 2.5 | 3.9 | 5.9 | µA | ENx = 1 V | 6 |
| EN1/2/3 pullup current | IENX2 | 5.1 | 6.9 | 9.2 | µA | ENx = 1.5 V | 6 |
| Hysteresis current | IENhys | 2.6 | 3 | 3.3 | µA | 6 | |
| Soft-start charging current | ISSX | 3.9 | 5.2 | 6.5 | µA | 6 | |
| Minimum on-time | tON_MIN | 50 | 75 | 110 | ns | 6 | |
| Error amplifier transconductance | Gm_EA | 140 | 300 | 450 | µs | -2 µA < ICOMPX < 2 µA | 6 |
| Buck1 peak inductor current limit | ILIMIT1 | 4.3 | 5.4 | 6.5 | A | 6 | |
| Buck1 low-side sink current limit | ILIMITSINK1 | 0.7 | 1.3 | 1.8 | A | 6 | |
| Buck2/buck3 peak inductor current limit | ILIMIT2/3 | 2.55 | 3.3 | 3.9 | A | 6 | |
| Buck2/buck3 low-side sink current limit | ILIMITSINK2/3 | 0.5 | 1 | 1.4 | A | 6 | |
| Switching frequency | FSW | 430 | 500 | 560 | kHz | ROSC = 88.7 kΩ | 7 |
| Switching frequency range | FSW_range | 200 | 2300 | kHz | 7 | ||
| Clock sync frequency range | FSYNC | 200 | 2300 | kHz | 7 | ||
| SDA, SCL input current | II | -10 | 10 | µA | VI = 0.4 to 4.5 V | 7 | |
| Data hold time | tHD_DAT | 0 | 0.9 | µs | 7 | ||
| Rise time of SCL signal | tRCL | 300 | ns | Capacitance of one bus line (pF) | 7 | ||
| Rise time of SCL signal after a repeated START condition and after an acknowledge bit | tRCL1 | 300 | ns | Capacitance of one bus line (pF) | 7 | ||
| Fall time of SCL signal | tFCL | 300 | ns | Capacitance of one bus line (pF) | 7 | ||
| Rise time of SDA signal | tRDA | 300 | ns | Capacitance of one bus line (pF) | 7 | ||
| Fall time of SDA signal | tFDA | 300 | ns | Capacitance of one bus line (pF) | 7 | ||
| Thermal resistance, junction-to-ambient (RHB 32-pin VQFN) | RθJA | 33.3 | °C/W | 5 | |||
| Thermal resistance, junction-to-case (top) (RHB 32-pin VQFN) | RθJC(top) | 25.7 | °C/W | 5 | |||
| Thermal resistance, junction-to-board (RHB 32-pin VQFN) | RθJB | 7.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter (RHB 32-pin VQFN) | ψJT | 0.3 | °C/W | 5 | |||
| Junction-to-board characterization parameter (RHB 32-pin VQFN) | ψJB | 7.3 | °C/W | 5 | |||
| Thermal resistance, junction-to-case (bottom) (RHB 32-pin VQFN) | RθJC(bot) | 2.1 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS65263QRHBTQ1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65263qrhbtq1-etched.step/tps65263qrhbtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65263qrhbtq1.step/tps65263qrhbtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
e578b0a6a290a0b9, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).