component
LMR51606YDBVR
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLMR51606YDBVR
TEXAS INSTRUMENTS · Global Sourcing Parts · SOT-23-6
LMR51606YDBVR from TEXAS INSTRUMENTS, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB | passive | Bootstrap capacitor connection for the high-side FET driver; a 100nF quality capacitor is connected between this pin and SW. |
| 2 | GND | power_in | Power ground pin, internally connected to the low-side FET source; connect to system ground and to the ground side of CIN and COUT, keeping the connection to CIN short. |
| 3 | FB | input | Converter feedback input; a resistor divider connected here sets the output voltage, and this pin must not be shorted to ground during operation. |
| 4 | EN | input | Precision enable input that must not be left open or floating; high turns the converter on and low turns it off, it may be tied to VIN, and an external divider allows an adjustable UVLO. |
| 5 | VIN | power_in | Input supply pin for the internal bias LDO and high-side FET, operating over 4 V to 65 V; the input bypass capacitor CIN must be connected directly between this pin and GND. |
| 6 | SW | output | Converter switching output, internally connected to the high-side FET source and low-side FET drain; connects to the power inductor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | SOT-23-6 |
| Category | Global Sourcing Parts |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | VIN | -0.3 | 70 | V | 4 | ||
| EN to GND | EN | -0.3 | V | max printed as VIN + 0.3 V | 4 | ||
| FB to GND | FB | -0.3 | 5.5 | V | 4 | ||
| SW to GND | SW | -0.3 | 70 | V | 4 | ||
| SW to GND transient | SW | -5 | 70 | V | transient less than 10 ns | 4 | |
| CBOOT to SW | CBOOT | -0.3 | 5.5 | V | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| VIN input voltage | VIN | 4 | 65 | V | VIN to GND | 4 | |
| EN input voltage | EN | 0 | V | max printed as VIN | 4 | ||
| FB voltage | FB | 0 | 4.5 | V | 4 | ||
| Output voltage | VOUT | 0.8 | 28 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Quiescent current, non-switching, PFM | IQ(VIN) | 26.5 | 40 | µA | VEN = 3 V, PFM model only | 5 | |
| Shutdown supply current | ISD(VIN) | 0.8 | 3 | µA | VEN = 0 V | 5 | |
| EN rising threshold (enable switching) | VEN(R) | 1.1 | 1.227 | 1.36 | V | EN rising, enables switching | 5 |
| EN falling threshold (disable switching) | VEN(F) | 0.85 | 1 | 1.15 | V | EN falling, disables switching | 5 |
| Reference voltage | Vfb | 0.788 | 0.8 | 0.812 | V | 5 | |
| Switching frequency, CCM, Y version | fSW(CCM) | 0.935 | 1.1 | 1.265 | Mhz | CCM operation, Y version | 5 |
| High-side peak current limit, LMR51606 | IHS_PK(OC) | 0.8 | 1.1 | 1.4 | A | LMR51606 | 6 |
| Low-side valley current limit, LMR51606 | ILS_V(OC) | 0.62 | 0.8 | 0.98 | A | LMR51606 | 6 |
| VOUT adjustment regulation accuracy | VOUT | -1.5 | 2.5 | % | PFM operation, VIN = 24 V, IOUT = 0 A to full load, deviation from nominal VOUT | 6 | |
| Maximum duty cycle | DMAX | 98 | % | 6 | |||
| Thermal resistance, junction-to-ambient | RθJA | 147.8 | °C/W | JESD 51-7, 4-layer JEDEC board | 5 | ||
| Thermal resistance, junction-to-ambient (effective, EVM) | RθJA(Effective) | 95 | °C/W | EVM | 5 | ||
| Thermal resistance, junction-to-case (top) | RθJC(top) | 71.1 | °C/W | 5 | |||
| Thermal resistance, junction-to-board | RθJB | 36.6 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 14.2 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 36.4 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
LMR51606YDBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
lmr51606ydbvr-etched.step/lmr51606ydbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr51606ydbvr.step/lmr51606ydbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (33 pp, sha256
5c1fcf38e7a0045e, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).