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LTC721XT5

Public Made by Adom

by adom

Linearin Operational Amplifier, SOT-23-5L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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LTC721XT5

Linearin · Operational Amplifier · SOT-23-5L

LTC721XT5 from Linearin, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Amplifier output; the datasheet states the LTC72x can safely drive capacitive loads of up to 500 pF in any configuration.
2 -VS power_in Negative power supply, normally tied to ground; it may be tied to another voltage as long as the voltage between VS+ and VS- is 2.0 V to 5.5 V.
3 +IN input Non-inverting amplifier input with a voltage range from (VS- - 0.1 V) to (VS+ + 0.1 V).
4 -IN input Inverting amplifier input with a voltage range from (VS- - 0.1 V) to (VS+ + 0.1 V).
5 +VS power_in Positive power supply, specified from 2.0 V to 5.5 V (split supplies allowed while VS+ to VS- stays within 2.0 V to 5.5 V).

Key specifications

Parameter Value
Manufacturer Linearin
Package SOT-23-5L
Category Operational Amplifier/Comparator
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VS+ to VS- 10 V 3
Signal input terminals voltage (relative to VS- / VS+) -0.5 0.5 V 3
Signal input terminals current -10 10 mA 3
Storage temperature range Tstg -65 150 ℃ 3
Junction temperature TJ 150 ℃ 3
Lead temperature range (soldering) 260 ℃ 10 sec soldering 3
ESD Human body model (HBM) -5000 5000 V MIL-STD-883J / Method 3015.9 3
ESD Charged device model (CDM) -2000 2000 V ESDA/JEDEC JS-002-2014 3
ESD Machine model (MM) -250 250 V JESD22-A115C 3
Input offset voltage VOS -3 0.5 3 mV 4
Offset voltage drift VOS TC -3 1 3 μV/℃ TA = −40 to +125 ℃ 4
Power supply rejection ratio PSRR 95 110 dB VS = 2.0 to 5.5 V, VCM < VS+ − 2V 4
Power supply rejection ratio PSRR 82 dB TA = −40 to +125 ℃ 4
Input bias current IB 150 pA TA = +85 ℃ 4
Input bias current IB 500 pA TA = +125 ℃ 4
Common-mode voltage range (relative to VS- / VS+) VCM -0.1 0.1 V 4
Common-mode rejection ratio CMRR 68 84 dB VS = 5.5 V, VCM = −0.1 to 5.6 V 4
Common-mode rejection ratio CMRR 65 dB VCM = 0 to 5.3 V, TA = −40 to +125 ℃ 4
Common-mode rejection ratio CMRR 65 78 dB VS = 2.0 V, VCM = −0.1 to 2.1 V 4
Common-mode rejection ratio CMRR 62 dB VCM = 0 to 1.8 V, TA = −40 to +125 ℃ 4
Open-loop voltage gain AVOL 97 105 dB RL = 10 kΩ, VO = 0.05 to 3.5 V 4
Open-loop voltage gain AVOL 87 dB TA = −40 to +125 ℃ 4
Open-loop voltage gain AVOL 85 92 dB RL = 600 Ω, VO = 0.15 to 3.5 V 4
Open-loop voltage gain AVOL 75 dB TA = −40 to +125 ℃ 4
High output voltage swing (headroom below VS+) VOH 12 8 mV RL = 10 kΩ 5
High output voltage swing (headroom below VS+) VOH 180 125 mV RL = 600 Ω 5
Low output voltage swing (headroom above VS-) VOL 5.5 8 mV RL = 10 kΩ 5
Low output voltage swing (headroom above VS-) VOL 88 130 mV RL = 600 Ω 5
Short-circuit current ISC -85 70 mA 5
Operating supply voltage VS 1.8 5.5 V TA = 0 to +70 ℃ 5
Operating supply voltage VS 2 5.5 V TA = −40 to +125 ℃ 5
Operating temperature range TA -40 125 ℃ 5
Quiescent current (per amplifier) IQ 615 740 μA VS = 2.0 V 5
Quiescent current (per amplifier) IQ 780 940 μA VS = 5.5 V 5
Package thermal resistance, junction-to-ambient θJA 190 ℃/W SOT23-5L 5
Input offset current IOS 1 pA 4
Input voltage noise Vn 3.7 μVP-P f = 0.1 to 10 Hz 4
Input voltage noise density en 8 nV/√Hz f = 1 kHz 4
Input current noise density In 5 fA/√Hz f = 1 kHz 4
Input capacitance, differential CIN 2 pF Differential 4
Input capacitance, common mode CIN 3.5 pF Common mode 4
Gain bandwidth product GBW 11 MHz 4
Slew rate SR 11.5 V/μs G = +1, CL = 100 pF, VO = 1.5 to 3.5 V 4
Total harmonic distortion + noise THD+N 0.0005 % G = +1, f = 1 kHz, VO = 0.5 VRMS 4
Settling time to 0.1% tS 0.26 μs To 0.1%, G = +1, 1V step 4
Settling time to 0.01% tS 0.34 μs To 0.01%, G = +1, 1V step 4
Overload recovery time tOR 0.3 μs VIN * Gain > VS 4

CAD (KiCad official)

  • Symbol: LTC721XT5
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5L (KiCad packages3D, STEP)
  • 3D model files: ltc721xt5-etched.step / ltc721xt5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc721xt5.step / ltc721xt5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Linearin datasheet (24 pp, sha256 51e76ddb80b2c56c, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF