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SN74ALS04BN

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Texas Instruments Inverters, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74ALS04BN

Texas Instruments · Inverters · PDIP-14

SN74ALS04BN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of inverter 1, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
2 1Y output Output Y of inverter 1, the logic inverse of input 1A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
3 2A input Input A of inverter 2, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
4 2Y output Output Y of inverter 2, the logic inverse of input 2A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
5 3A input Input A of inverter 3, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
6 3Y output Output Y of inverter 3, the logic inverse of input 3A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
7 GND power_in Ground pin shared by the six inverters; the datasheet gives no separate electrical limit for this pin.
8 4Y output Output Y of inverter 4, the logic inverse of input 4A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
9 4A input Input A of inverter 4, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
10 5Y output Output Y of inverter 5, the logic inverse of input 5A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
11 5A input Input A of inverter 5, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
12 6Y output Output Y of inverter 6, the logic inverse of input 6A; VOL is at most 0.4 V at IOL = 4 mA with VCC = 4.5 V.
13 6A input Input A of inverter 6, which drives Y = A; recommended VIH is at least 2 V and VIL at most 0.8 V, with an absolute maximum input voltage of 7 V.
14 VCC power_in Supply pin; recommended VCC is 4.5 V to 5.5 V (5 V nominal) with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V Applies over −55°C to 70°C (footnote ‡) 2
High-level output current IOH -0.4 mA 2
Low-level output current IOL 8 mA 2
Operating free-air temperature TA 0 70 °C SN74ALS04B 2
Supply voltage VCC 7 V 2
Input voltage VI 7 V 2
Operating free-air temperature range TA 0 70 °C SN74ALS04B 2
Storage temperature range Tstg -65 150 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = −18 mA 2
Low-level output voltage VOL 0.25 0.4 V VCC = 4.5 V, IOL = 4 mA 2
Low-level output voltage VOL 0.35 0.5 V VCC = 4.5 V, IOL = 8 mA 2
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.1 mA VCC = 5.5 V, VI = 0.4 V 2
Short-circuit output current IO -30 -112 mA VCC = 5.5 V, VO = 2.25 V 2
Supply current (outputs high) ICCH 0.65 1.1 mA VCC = 5.5 V, VI = 0 2
Supply current (outputs low) ICCL 2.9 4.2 mA VCC = 5.5 V, VI = 4.5 V 2
Propagation delay time, low-to-high-level output tPLH 3 11 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay time, high-to-low-level output tPHL 2 8 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3

CAD (KiCad official)

  • Symbol: SN74ALS04BN
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74als04bn-etched.step / sn74als04bn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74als04bn.step / sn74als04bn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 07a4a6a3194e7a58, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF