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STM32F051K8T7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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STM32F051K8T7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM32F051K8T7 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital power supply; the digital and I/O supply range is VDD = 2.0 V to 3.6 V.
2 PF0-OSC_IN bidirectional 5 V-tolerant (FT) I/O that is also the OSC_IN input of the 4 to 32 MHz crystal oscillator.
3 PF1-OSC_OUT bidirectional 5 V-tolerant (FT) I/O that is also the OSC_OUT output of the 4 to 32 MHz crystal oscillator.
4 NRST bidirectional Active-low bidirectional reset pin with embedded weak pull-up, acting as device reset input and internal reset output.
5 VDDA power_in Analog power supply; VDDA may range from VDD up to 3.6 V.
6 PA0 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN0), also providing USART2_CTS, TIM2_CH1_ETR, COMP1_OUT and TSC_G1_IO1 alternate functions.
7 PA1 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN1), also providing USART2_RTS, TIM2_CH2, TSC_G1_IO2 and EVENTOUT functions.
8 PA2 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN2), also providing USART2_TX, TIM2_CH3, TIM15_CH1, COMP2_OUT and TSC_G1_IO3 functions.
9 PA3 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN3), also providing USART2_RX, TIM2_CH4, TIM15_CH2 and TSC_G1_IO4 functions.
10 PA4 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN4), also providing SPI1_NSS, I2S1_WS, USART2_CK, TIM14_CH1, TSC_G2_IO1 and DAC_OUT1 functions.
11 PA5 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN5), also providing SPI1_SCK, I2S1_CK, CEC, TIM2_CH1_ETR and TSC_G2_IO2 functions.
12 PA6 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN6), also providing SPI1_MISO, I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT and TSC_G2_IO3 functions.
13 PA7 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN7), also providing SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, COMP2_OUT and TSC_G2_IO4 functions.
14 PB0 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN8), also providing TIM3_CH3, TIM1_CH2N, TSC_G3_IO2 and EVENTOUT functions.
15 PB1 bidirectional TTa 3.3 V-tolerant I/O directly connected to the ADC (ADC_IN9), also providing TIM3_CH4, TIM14_CH1, TIM1_CH3N and TSC_G3_IO3 functions.
16 VSS power_in Ground pin; per the package notes, the analog ground VSSA is connected to this pin on packages with fewer than 48 pins.
17 VDD power_in Digital power supply; the digital and I/O supply range is VDD = 2.0 V to 3.6 V.
18 PA8 bidirectional 5 V-tolerant (FT) I/O also providing USART1_CK, TIM1_CH1, EVENTOUT and MCO functions.
19 PA9 bidirectional 5 V-tolerant (FT) I/O also providing USART1_TX, TIM1_CH2, TIM15_BKIN and TSC_G4_IO1 functions.
20 PA10 bidirectional 5 V-tolerant (FT) I/O also providing USART1_RX, TIM1_CH3, TIM17_BKIN and TSC_G4_IO2 functions.
21 PA11 bidirectional 5 V-tolerant (FT) I/O also providing USART1_CTS, TIM1_CH4, COMP1_OUT, TSC_G4_IO3 and EVENTOUT functions.
22 PA12 bidirectional 5 V-tolerant (FT) I/O also providing USART1_RTS, TIM1_ETR, COMP2_OUT, TSC_G4_IO4 and EVENTOUT functions.
23 PA13 (SWDIO) bidirectional 5 V-tolerant (FT) I/O that is configured as SWDIO after reset with the internal pull-up enabled, also providing IR_OUT.
24 PA14 (SWCLK) bidirectional 5 V-tolerant (FT) I/O that is configured as SWCLK after reset with the internal pull-down enabled, also providing USART2_TX.
25 PA15 bidirectional 5 V-tolerant (FT) I/O also providing SPI1_NSS, I2S1_WS, USART2_RX, TIM2_CH1_ETR and EVENTOUT functions.
26 PB3 bidirectional 5 V-tolerant (FT) I/O also providing SPI1_SCK, I2S1_CK, TIM2_CH2, TSC_G5_IO1 and EVENTOUT functions.
27 PB4 bidirectional 5 V-tolerant (FT) I/O also providing SPI1_MISO, I2S1_MCK, TIM3_CH1, TSC_G5_IO2 and EVENTOUT functions.
28 PB5 bidirectional 5 V-tolerant (FT) I/O also providing SPI1_MOSI, I2S1_SD, I2C1_SMBA, TIM16_BKIN and TIM3_CH2 functions.
29 PB6 bidirectional 5 V-tolerant (FTf) I/O that is Fast Mode Plus capable, also providing I2C1_SCL, USART1_TX, TIM16_CH1N and TSC_G5_IO3 functions.
30 PB7 bidirectional 5 V-tolerant (FTf) I/O that is Fast Mode Plus capable, also providing I2C1_SDA, USART1_RX, TIM17_CH1N and TSC_G5_IO4 functions.
31 BOOT0 input Dedicated BOOT0 pin used for boot memory selection.
32 VSS power_in Ground pin.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM32F051K8T7
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f051k8t7-etched.step / stm32f051k8t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f051k8t7.step / stm32f051k8t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (122 pp, sha256 80848a22804e56d8, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF