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STM8S105K4T3C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM8S105K4T3C
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STM8S105K4T3C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NRST | bidirectional | Device reset pin (listed as I/O in the pin table), with its characteristics given in the NRST pin characteristics section. |
| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that also serves as the resonator/crystal input OSCIN, or the external clock signal input when option bit EXTCLK is set to 1. |
| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that also serves as the resonator/crystal output OSCOUT for the external crystal connected to OSCIN/OSCOUT. |
| 4 | VSS | power_in | Digital ground. |
| 5 | VCAP | passive | Connection for the 1.8 V internal regulator capacitor. |
| 6 | VDD | power_in | Digital power supply; the device operates from 2.95 V to 5.5 V. |
| 7 | VDDIO_1 | power_in | I/O power supply. |
| 8 | PF4/AIN12 | bidirectional | Port F4 I/O with analog input AIN12, which is not selectable in ADC scan mode or with the analog watchdog; a pull-up is applied during reset and the pin is input floating after reset release. |
| 9 | VDDA | power_in | Analog power supply. |
| 10 | VSSA | power_in | Analog ground. |
| 11 | PB5/AIN5 | bidirectional | Port B5 I/O with analog input AIN5; when option AFR6 is set, this pin becomes the I2C_SDA alternate function. |
| 12 | PB4/AIN4 | bidirectional | Port B4 I/O with analog input AIN4; when option AFR6 is set, this pin becomes the I2C_SCL alternate function. |
| 13 | PB3/AIN3 | bidirectional | Port B3 I/O with analog input AIN3; when option AFR5 is set, this pin becomes the TIM1_ETR alternate function. |
| 14 | PB2/AIN2 | bidirectional | Port B2 I/O with analog input AIN2; when option AFR5 is set, this pin becomes the TIM1_CH3N alternate function. |
| 15 | PB1/AIN1 | bidirectional | Port B1 I/O with analog input AIN1; when option AFR5 is set, this pin becomes the TIM1_CH2N alternate function. |
| 16 | PB0/AIN0 | bidirectional | Port B0 I/O with analog input AIN0; when option AFR5 is set, this pin becomes the TIM1_CH1N alternate function. |
| 17 | PE5/SPI_NSS | bidirectional | Port E5 I/O that serves as the SPI master/slave select input SPI_NSS. |
| 18 | PC1/TIM1_CH1/UART2_CK | bidirectional | Port C1 high sink I/O that serves as TIM1 channel 1 or the UART2 synchronous clock output UART2_CK. |
| 19 | PC2/TIM1_CH2 | bidirectional | Port C2 high sink I/O that serves as TIM1 channel 2. |
| 20 | PC3/TIM1_CH3 | bidirectional | Port C3 high sink I/O that serves as TIM1 channel 3. |
| 21 | PC4/TIM1_CH4 | bidirectional | Port C4 high sink I/O that serves as TIM1 channel 4. |
| 22 | PC5/SPI_SCK | bidirectional | Port C5 high sink I/O that serves as the SPI clock SPI_SCK. |
| 23 | PC6/SPI_MOSI | bidirectional | Port C6 high sink I/O that serves as the SPI master out / slave in line SPI_MOSI. |
| 24 | PC7/SPI_MISO | bidirectional | Port C7 high sink I/O that serves as the SPI master in / slave out line SPI_MISO. |
| 25 | PD0/TIM3_CH2 | bidirectional | Port D0 high sink I/O that serves as TIM3 channel 2; option AFR3 remaps it to TIM1_BKIN and option AFR2 remaps it to CLK_CCO (AFR2 has priority). |
| 26 | PD1/SWIM | bidirectional | Port D1 high sink I/O that serves as the SWIM single-wire data interface; the pin is in input pull-up during reset and after internal reset release. |
| 27 | PD2/TIM3_CH1 | bidirectional | Port D2 high sink I/O that serves as TIM3 channel 1; option AFR1 remaps it to TIM2_CH3. |
| 28 | PD3/TIM2_CH2 | bidirectional | Port D3 high sink I/O that serves as TIM2 channel 2; option AFR0 remaps it to the ADC_ETR input. |
| 29 | PD4/TIM2_CH1 | bidirectional | Port D4 high sink I/O that serves as TIM2 channel 1; option AFR7 makes it the BEEP output. |
| 30 | PD5/UART2_TX | bidirectional | Port D5 I/O that serves as the UART2 data transmit output UART2_TX. |
| 31 | PD6/UART2_RX | bidirectional | Port D6 I/O that serves as the UART2 data receive input UART2_RX. |
| 32 | PD7/TLI | bidirectional | Port D7 I/O that serves as the top level interrupt input TLI; option AFR4 remaps it to TIM1_CH4. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
STM8S105K4T3C - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm8s105k4t3c-etched.step/stm8s105k4t3c-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm8s105k4t3c.step/stm8s105k4t3c.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (121 pp, sha256
b1007bc27bb78327, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).