component
74LV4094PW
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74LV4094PW
Nexperia · Shift Registers · TSSOP-16
74LV4094PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input; data is transferred from the shift register to the storage register when STR is HIGH. |
| 2 | D | input | Serial data input to the 8-stage shift register; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 3 | CP | input | Clock input; data is shifted into the shift register on LOW-to-HIGH transitions of CP. |
| 4 | QP0 | tri_state | Parallel 3-state output from storage register stage 0; enters high-impedance OFF-state when OE is LOW. |
| 5 | QP1 | tri_state | Parallel 3-state output from storage register stage 1; enters high-impedance OFF-state when OE is LOW. |
| 6 | QP2 | tri_state | Parallel 3-state output from storage register stage 2; enters high-impedance OFF-state when OE is LOW. |
| 7 | QP3 | tri_state | Parallel 3-state output from storage register stage 3; enters high-impedance OFF-state when OE is LOW. |
| 8 | GND | power_in | Ground supply voltage; 0 V reference for all voltages. |
| 9 | QS1 | output | Serial output; data is available on LOW-to-HIGH transitions of CP to allow cascading when clock edges are fast. |
| 10 | QS2 | output | Serial output; the same data appears on the next HIGH-to-LOW transition of CP to allow cascading when clock edges are slow. |
| 11 | QP7 | tri_state | Parallel 3-state output from storage register stage 7; enters high-impedance OFF-state when OE is LOW. |
| 12 | QP6 | tri_state | Parallel 3-state output from storage register stage 6; enters high-impedance OFF-state when OE is LOW. |
| 13 | QP5 | tri_state | Parallel 3-state output from storage register stage 5; enters high-impedance OFF-state when OE is LOW. |
| 14 | QP4 | tri_state | Parallel 3-state output from storage register stage 4; enters high-impedance OFF-state when OE is LOW. |
| 15 | OE | input | Output enable input; parallel outputs are active when HIGH and go to high-impedance OFF-state when LOW, without changing the register states. |
| 16 | VCC | power_in | Supply voltage; recommended operating range is 1.0 V to 3.6 V, with an absolute maximum of +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 5 | |
| output clamping current | IOK | -50 | 50 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 5 | |
| supply current | ICC | 50 | mA | 5 | |||
| ground current | IGND | -50 | mA | 5 | |||
| storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 5 | ||
| supply voltage | VCC | 1 | 3.3 | 3.6 | V | 5 | |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 5 | |
| input transition rise and fall rate | Δt/ΔV | 500 | ns/V | VCC = 1.0 V to 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 200 | ns/V | VCC = 2.0 V to 2.7 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 100 | ns/V | VCC = 2.7 V to 3.6 V | 5 | ||
| HIGH-level input voltage | VIH | 1.4 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| HIGH-level input voltage | VIH | 2 | V | -40 °C to +125 °C; VCC = 2.7 V to 3.6 V | 6 | ||
| LOW-level input voltage | VIL | 0.6 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| LOW-level input voltage | VIL | 0.8 | V | -40 °C to +125 °C; VCC = 2.7 V to 3.6 V | 6 | ||
| HIGH-level output voltage | VOH | 1.8 | V | -40 °C to +125 °C; VI = VIH or VIL; all pins; IO = -100 μA; VCC = 2.0 V | 6 | ||
| HIGH-level output voltage | VOH | 2.5 | V | -40 °C to +125 °C; VI = VIH or VIL; all pins; IO = -100 μA; VCC = 2.7 V | 6 | ||
| HIGH-level output voltage | VOH | 2.8 | V | -40 °C to +125 °C; VI = VIH or VIL; all pins; IO = -100 μA; VCC = 3.0 V | 6 | ||
| HIGH-level output voltage | VOH | 2.2 | V | -40 °C to +125 °C; VI = VIH or VIL; pins QPn; IO = -6 mA; VCC = 3.0 V | 6 | ||
| LOW-level output voltage | VOL | 0.2 | V | -40 °C to +125 °C; VI = VIH or VIL; all pins; IO = 100 μA; VCC = 2.0 V | 6 | ||
| LOW-level output voltage | VOL | 0.5 | V | -40 °C to +125 °C; VI = VIH or VIL; pins QPn; IO = 6 mA; VCC = 3.0 V | 6 | ||
| input leakage current | II | -1 | 1 | μA | -40 °C to +125 °C; VI = VCC or GND; VCC = 3.6 V | 6 | |
| OFF-state output current | IOZ | -10 | 10 | μA | -40 °C to +125 °C; VI = VIH or VIL; VO = VCC or GND; VCC = 3.6 V | 6 | |
| supply current | ICC | 160 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 3.6 V | 6 | ||
| additional supply current | ΔICC | 850 | μA | -40 °C to +125 °C; per input; VI = VCC - 0.6 V; VCC = 2.7 V to 3.6 V | 6 | ||
| CP to QS1 propagation delay | tpd | 70 | ns | -40 °C to +125 °C; CP to QS1; VCC = 2.0 V; CL = 50 pF | 7 | ||
| CP to QS1 propagation delay | tpd | 51 | ns | -40 °C to +125 °C; CP to QS1; VCC = 2.7 V; CL = 50 pF | 7 | ||
| CP to QS1 propagation delay | tpd | 41 | ns | -40 °C to +125 °C; CP to QS1; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| CP to QS2 propagation delay | tpd | 36 | ns | -40 °C to +125 °C; CP to QS2; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| CP to QPn propagation delay | tpd | 90 | ns | -40 °C to +125 °C; CP to QPn; VCC = 2.0 V; CL = 50 pF | 7 | ||
| CP to QPn propagation delay | tpd | 66 | ns | -40 °C to +125 °C; CP to QPn; VCC = 2.7 V; CL = 50 pF | 7 | ||
| CP to QPn propagation delay | tpd | 53 | ns | -40 °C to +125 °C; CP to QPn; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| STR to QPn propagation delay | tpd | 82 | ns | -40 °C to +125 °C; STR to QPn; VCC = 2.0 V; CL = 50 pF | 7 | ||
| STR to QPn propagation delay | tpd | 60 | ns | -40 °C to +125 °C; STR to QPn; VCC = 2.7 V; CL = 50 pF | 7 | ||
| STR to QPn propagation delay | tpd | 48 | ns | -40 °C to +125 °C; STR to QPn; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| OE to QPn enable time | ten | 77 | ns | -40 °C to +125 °C; OE to QPn; VCC = 2.0 V; CL = 50 pF | 7 | ||
| OE to QPn enable time | ten | 56 | ns | -40 °C to +125 °C; OE to QPn; VCC = 2.7 V; CL = 50 pF | 7 | ||
| OE to QPn enable time | ten | 45 | ns | -40 °C to +125 °C; OE to QPn; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| OE to QPn disable time | tdis | 49 | ns | -40 °C to +125 °C; OE to QPn; VCC = 2.0 V; CL = 50 pF | 7 | ||
| OE to QPn disable time | tdis | 37 | ns | -40 °C to +125 °C; OE to QPn; VCC = 2.7 V; CL = 50 pF | 7 | ||
| OE to QPn disable time | tdis | 30 | ns | -40 °C to +125 °C; OE to QPn; VCC = 3.0 V to 3.6 V; CL = 50 pF | 7 | ||
| CP pulse width HIGH or LOW | tW | 41 | ns | -40 °C to +125 °C; CP HIGH or LOW; VCC = 2.0 V | 8 | ||
| CP pulse width HIGH or LOW | tW | 30 | ns | -40 °C to +125 °C; CP HIGH or LOW; VCC = 2.7 V | 8 | ||
| CP pulse width HIGH or LOW | tW | 24 | ns | -40 °C to +125 °C; CP HIGH or LOW; VCC = 3.0 V to 3.6 V | 8 | ||
| D to CP set-up time | tsu | 26 | ns | -40 °C to +125 °C; D to CP; see Fig. 9; VCC = 2.0 V | 8 | ||
| D to CP set-up time | tsu | 19 | ns | -40 °C to +125 °C; D to CP; see Fig. 9; VCC = 2.7 V | 8 | ||
| D to CP set-up time | tsu | 15 | ns | -40 °C to +125 °C; D to CP; see Fig. 9; VCC = 3.0 V to 3.6 V | 8 | ||
| CP to STR set-up time | tsu | 51 | ns | -40 °C to +125 °C; CP to STR; see Fig. 7; VCC = 2.0 V | 8 | ||
| CP to STR set-up time | tsu | 38 | ns | -40 °C to +125 °C; CP to STR; see Fig. 7; VCC = 2.7 V | 8 | ||
| CP to STR set-up time | tsu | 30 | ns | -40 °C to +125 °C; CP to STR; see Fig. 7; VCC = 3.0 V to 3.6 V | 8 | ||
| D to CP hold time | th | 5 | ns | -40 °C to +125 °C; D to CP; see Fig. 9; VCC = 2.0 V | 8 | ||
| maximum frequency | fmax | 12 | MHz | -40 °C to +125 °C; CP; see Fig. 6; VCC = 2.0 V | 8 | ||
| maximum frequency | fmax | 16 | MHz | -40 °C to +125 °C; CP; see Fig. 6; VCC = 2.7 V | 8 | ||
| maximum frequency | fmax | 20 | MHz | -40 °C to +125 °C; CP; see Fig. 6; VCC = 3.0 V to 3.6 V | 8 |
CAD (KiCad official)
- Symbol:
74LV4094PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74lv4094pw-etched.step/74lv4094pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74lv4094pw.step/74lv4094pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
4b6bf378275a9969, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).