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LMK04828SNKDREP

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

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LMK04828SNKDREP

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · WQFN-64-EP(9x9)

LMK04828SNKDREP from Texas Instruments, in a WQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DCLKout0 output Programmable device clock output 0 (true side of the differential pair; complement is pin 2).
2 DCLKout0* output Complementary side of programmable device clock output 0.
3 SDCLKout1 output Programmable SYSREF or device clock output 1 (true side).
4 SDCLKout1* output Complementary side of programmable SYSREF or device clock output 1.
5 RESET/GPO input CMOS device reset input, or general-purpose output (GPO) when so programmed.
6 SYNC/SYSREF_REQ input CMOS synchronization input, or SYSREF_REQ for requesting continuous SYSREF.
7 NC unconnected Do not connect; this pin must be left floating.
8 NC unconnected Do not connect; this pin must be left floating.
9 NC unconnected Do not connect; this pin must be left floating.
10 Vcc1_VCO power_in Power supply for the VCO LDO.
11 LDObyp1 passive Analog LDO bypass, bypassed to ground with a 10-µF capacitor.
12 LDObyp2 passive Analog LDO bypass, bypassed to ground with a 0.1-µF capacitor.
13 SDCLKout3 output Programmable SYSREF or device clock output 3 (true side).
14 SDCLKout3* output Complementary side of programmable SYSREF or device clock output 3.
15 DCLKout2 output Programmable device clock output 2 (true side).
16 DCLKout2* output Complementary side of programmable device clock output 2.
17 Vcc2_CG1 power_in Power supply for clock outputs 2 and 3.
18 CS* input CMOS chip select for the SPI interface.
19 SCK input CMOS SPI clock.
20 SDIO bidirectional CMOS SPI data.
21 Vcc3_SYSREF power_in Power supply for the SYSREF divider and SYNC.
22 SDCLKout5 output Programmable SYSREF or device clock output 5 (true side).
23 SDCLKout5* output Complementary side of programmable SYSREF or device clock output 5.
24 DCLKout4 output Programmable device clock output 4 (true side).
25 DCLKout4* output Complementary side of programmable device clock output 4.
26 Vcc4_CG2 power_in Power supply for clock outputs 4, 5, 6 and 7.
27 DCLKout6 output Programmable device clock output 6 (true side).
28 DCLKout6* output Complementary side of programmable device clock output 6.
29 SDCLKout7 output Programmable SYSREF or device clock output 7 (true side).
30 SDCLKout7* output Complementary side of programmable SYSREF or device clock output 7.
31 Status_LD1 bidirectional Programmable status pin.
32 CPout1 output Charge pump 1 output.
33 Vcc5_DIG power_in Power supply for the digital circuitry.
34 CLKin1/Fin/FBCLKin input Reference clock input port 1 for PLL1; the same pin also serves as FBCLKin (external feedback, 0-delay mode) or Fin (external VCO input, external VCO mode).
35 CLKin1*/Fin*/FBCLKin* input Complementary input for CLKin1, FBCLKin or Fin.
36 Vcc6_PLL1 power_in Power supply for PLL1, charge pump 1 and the holdover DAC.
37 CLKin0 input Reference clock input port 0 for PLL1 (true side).
38 CLKin0* input Complementary reference clock input port 0 for PLL1.
39 Vcc7_OSCout power_in Power supply for the OSCout port.
40 OSCout/CLKin2 bidirectional Programmable buffered output of the OSCin port; the same pin can also serve as reference Input Port 2 (CLKin2) for PLL1.
41 OSCout*/CLKin2* bidirectional Complementary programmable buffered OSCin output, or complementary CLKin2 reference input for PLL1.
42 Vcc8_OSCin power_in Power supply for OSCin.
43 OSCin input Feedback to PLL1 and reference input to PLL2; AC-coupled.
44 OSCin* input Complementary OSCin input; feedback to PLL1 and reference input to PLL2, AC-coupled.
45 Vcc9_CP2 power_in Power supply for the PLL2 charge pump.
46 CPout2 output Charge pump 2 output.
47 Vcc10_PLL2 power_in Power supply for PLL2.
48 Status_LD2 bidirectional Programmable status pin.
49 SDCLKout9 output Programmable SYSREF or device clock output 9 (true side).
50 SDCLKout9* output Complementary side of programmable SYSREF or device clock output 9.
51 DCLKout8 output Programmable device clock output 8 (true side).
52 DCLKout8* output Complementary side of programmable device clock output 8.
53 Vcc11_CG3 power_in Power supply for clock outputs 8, 9, 10 and 11.
54 DCLKout10 output Programmable device clock output 10 (true side).
55 DCLKout10* output Complementary side of programmable device clock output 10.
56 SDCLKout11 output Programmable SYSREF or device clock output 11 (true side).
57 SDCLKout11* output Complementary side of programmable SYSREF or device clock output 11.
58 CLKin_SEL0 bidirectional Programmable status pin.
59 CLKin_SEL1 bidirectional Programmable status pin.
60 SDCLKout13 output Programmable SYSREF or device clock output 13 (true side).
61 SDCLKout13* output Complementary side of programmable SYSREF or device clock output 13.
62 DCLKout12 output Programmable device clock output 12 (true side).
63 DCLKout12* output Complementary side of programmable device clock output 12.
64 Vcc12_CG0 power_in Power supply for clock outputs 0, 1, 12 and 13.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-64-EP(9x9)
Category Clock/Timing
Pins 65

CAD (KiCad official)

  • Symbol: LMK04828SNKDREP
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: WQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: lmk04828snkdrep-etched.step / lmk04828snkdrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk04828snkdrep.step / lmk04828snkdrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (98 pp, sha256 533243a632b68f6f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF