component
SST26VF040AT-104I
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MICROCHIP TECHNOLOGY / ATMEL Global Sourcing Parts, SOIC-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Contents
README
markdownSST26VF040AT-104I
MICROCHIP TECHNOLOGY / ATMEL · Global Sourcing Parts · SOIC-8-150mil
SST26VF040AT-104I from MICROCHIP TECHNOLOGY / ATMEL, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable: device is enabled by a high-to-low transition and CE# must remain low for the duration of any command sequence. |
| 2 | SO/SIO1 | bidirectional | Serial data output in SPI mode (SO) or serial data I/O 1 in SQI mode; data is shifted out on the falling edge of the serial clock and SO is the default after Power-on Reset or hardware Reset. |
| 3 | WP#/SIO2 | bidirectional | Write-Protect (works only in SPI single-bit and dual-bit Read mode, used with WPEN and IOC bits to prohibit writes to the Block Protection register) or serial data I/O 2 in quad mode. |
| 4 | VSS | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial data input in SPI mode (SI) or serial data I/O 0 in SQI mode; inputs are latched on the rising edge of the serial clock and SI is the default after Power-on Reset or hardware Reset. |
| 6 | SCK | input | Serial Clock: commands, addresses, or input data are latched on the rising edge and output data is shifted out on the falling edge. |
| 7 | RESET#/HOLD#/SIO3 | bidirectional | HOLD# temporarily stops serial communication (works only in SPI single-bit and dual-bit Read mode, must be tied high when not in use), RESET# resets the device when enabled via Configuration register bit 6, or serial data I/O 3 in quad mode. |
| 8 | VDD | power_in | Power supply voltage, 2.7V-3.6V or 2.3V-3.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MICROCHIP TECHNOLOGY / ATMEL |
| Package | SOIC-8-150mil |
| Category | Global Sourcing Parts |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Temperature under bias | -55 | 125 | °C | 40 | |||
| Storage temperature | -65 | 150 | °C | 40 | |||
| DC voltage on any pin to ground potential (min; max is VDD+0.5V) | -0.5 | V | -0.5V to VDD+0.5V | 40 | |||
| Transient voltage on any pin to ground (min; max is VDD+2.0V) | -2 | V | <20 ns; -2.0V to VDD+2.0V | 40 | |||
| Package power dissipation capability | 1 | W | TA = 25°C | 40 | |||
| Supply voltage (operating range) | VDD | 2.3 | 3.6 | V | Industrial | 40 | |
| Ambient temperature, Industrial | -40 | 85 | °C | Industrial | 40 | ||
| Read Current | IDDR1 | 8 | 15 | mA | VDD = VDD Max, CE# = 0.1 VDD/0.9 VDD @40 MHz, SO = Open | 42 | |
| Read Current | IDDR2 | 20 | mA | VDD = VDD Max, CE# = 0.1 VDD/0.9 VDD @104 MHz, SO = Open | 42 | ||
| Program and Erase Current | IDDW | 25 | mA | VDD Max | 42 | ||
| Standby Current | ISB1 | 15 | 30 | µA | CE# = VDD, VIN = VDD or VSS | 42 | |
| Standby Current | ISB2 | 50 | µA | CE# = VDD, VIN = VDD or VSS at 125°C | 42 | ||
| Deep Power-Down Current | IDPD1 | 8 | 20 | µA | CE# = VDD, VIN = VDD or VSS | 42 | |
| Deep Power-Down Current | IDPD2 | 30 | µA | CE# = VDD, VIN = VDD or VSS at 125°C | 42 | ||
| Input Leakage Current | ILI | 2 | µA | VIN = GND to VDD, VDD = VDD Max | 42 | ||
| Output Leakage Current | ILO | 2 | µA | VOUT = GND to VDD, VDD = VDD Max | 42 | ||
| Input Low Voltage | VIL | 0.8 | V | VDD = VDD Min | 42 | ||
| Input High Voltage (multiple of VDD) | VIH | 0.7 | VDD | VDD = VDD Max | 42 | ||
| Output Low Voltage | VOL | 0.2 | V | IOL = 100 µA, VDD = VDD Min | 42 | ||
| Output Pin Capacitance | COUT | 8 | pF | VOUT = 0V, TA = 25°C, f = 1 MHz | 42 | ||
| Input Capacitance | CIN | 6 | pF | VIN = 0V, TA = 25°C, f = 1 MHz | 42 | ||
| Endurance | NEND | 100000 | Cycles | JEDEC Standard A117 and AEC-Q100-005 | 42 | ||
| Data Retention | TDR | 100 | Years | JEDEC Standard A103 and AEC-Q100-005 | 42 | ||
| VDD Minimum to Read Operation | TPU-READ | 100 | µs | 40 | |||
| VDD Minimum to Write Operation | TPU-WRITE | 100 | µs | 40 | |||
| Power-Down Duration | TPD | 100 | ms | 40 | |||
| VDD Off | VOFF | 0.3 | V | 0V recommended | 40 | ||
| Sector Erase | TSE | 25 | ms | VDD = 2.3V-3.6V | 42 | ||
| Block Erase | TBE | 25 | ms | VDD = 2.3V-3.6V | 42 | ||
| Chip Erase | TSCE | 50 | ms | VDD = 2.3V-3.6V | 42 | ||
| Page Program | TPP | 1.5 | ms | VDD = 2.3V-3.6V | 42 | ||
| Program Security ID | TPSID | 1.5 | ms | VDD = 2.3V-3.6V | 42 | ||
| Write Suspend Latency | TWS | 25 | µs | VDD = 2.3V-3.6V | 42 | ||
| Configuration Register Write Latency | TCONFIG | 25 | ms | VDD = 2.3V-3.6V | 42 | ||
| Serial Clock Frequency | FCLK | 104 | MHz | 104 MHz column | 44 | ||
| Serial Clock Period | TCLK | 9.6 | ns | 104 MHz column | 44 | ||
| Serial Clock High Time | TSCKH | 4.5 | ns | 104 MHz column | 44 | ||
| Serial Clock Low Time | TSCKL | 4.5 | ns | 104 MHz column | 44 | ||
| CE# Active Setup Time | TCES | 5 | ns | 104 MHz column, relative to SCK | 44 | ||
| CE# Active Hold Time | TCEH | 5 | ns | 104 MHz column, relative to SCK | 44 | ||
| CE# Not Active Setup Time | TCHS | 5 | ns | 104 MHz column, relative to SCK | 44 | ||
| CE# Not Active Hold Time | TCHH | 5 | ns | 104 MHz column, relative to SCK | 44 | ||
| CE# High Time | TCPH | 12 | ns | 104 MHz column | 44 | ||
| CE# High-to-High Z Output | TCHZ | 12 | ns | 104 MHz column | 44 | ||
| HOLD# Low Setup Time | THLS | 5 | ns | 104 MHz column | 44 | ||
| HOLD# High Setup Time | THHS | 5 | ns | 104 MHz column | 44 | ||
| HOLD# Low Hold Time | THLH | 5 | ns | 104 MHz column | 44 | ||
| HOLD# High Hold Time | THHH | 5 | ns | 104 MHz column | 44 | ||
| HOLD# Low-to-High Z Output | THZ | 8 | ns | 104 MHz column | 44 | ||
| HOLD# High-to-Low Z Output | TLZ | 8 | ns | 104 MHz column | 44 | ||
| Data In Setup Time | TDS | 3 | ns | 104 MHz column | 44 | ||
| Data In Hold Time | TDH | 4 | ns | 104 MHz column | 44 | ||
| Output Hold from SCK Change | TOH | 0 | ns | 104 MHz column | 44 | ||
| Output Valid from SCK | TV | 8 | ns | 104 MHz column; printed 8/5 (30 pF/10 pF), 8 is the 30 pF value | 44 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 | 49 |
CAD (KiCad official)
- Symbol:
SST26VF040AT-104I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
- 3D model files:
sst26vf040at-104i-etched.step/sst26vf040at-104i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sst26vf040at-104i.step/sst26vf040at-104i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MICROCHIP TECHNOLOGY / ATMEL datasheet (73 pp, sha256
20b7245e058de3f5, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).