INA186A4IDDFR from Texas Instruments, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VS	power_in	Analog power supply pin, operating from 1.7 V to 5.5 V.
2	ENABLE	input	Enable pin: driving it to VS turns the device on, driving it to GND turns it off, reducing supply current and placing the output in high-impedance state, and it must be driven externally or connected to VS if unused.
3	REF	input	Reference input that enables bidirectional current sensing with an externally applied voltage, which must be within GND to VS.
4	GND	power_in	Analog ground pin.
5	OUT	output	Analog output giving the gained-up voltage difference from IN+ to IN-, offset by the voltage applied to REF; absolute limit is GND - 0.3 V to (VS) + 0.3 V.
6	NC	unconnected	No internal connection; can be left floating, grounded, or connected to supply.
7	IN+	input	Current-sense amplifier positive input; connect to bus voltage side of sense resistor for high-side applications or to load side for low-side applications.
8	IN-	input	Current-sense amplifier negative input; connect to load side of sense resistor for high-side applications or to ground side for low-side applications.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSOT-23-8
Category	Amplifiers/Comparators
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Common-mode rejection ratio	CMRR	120	150		dB	VSENSE = 0 mV, VIN+ = -0.1 V to 40 V, TA = -40°C to +125°C	5
Offset voltage, RTI	VOS	-3		50	µV	VS = 1.8 V, VSENSE = 0 mV	5
Offset drift, RTI	dVOS/dT		0.05	0.5	µV/°C	VSENSE = 0 mV, TA = -40°C to +125°C	5
Power-supply rejection ratio, RTI	PSRR	-1		10	µV/V	VSENSE = 0 mV, VS = 1.7 V to 5.5 V	5
Input bias current	IIB		0.5	3	nA	VSENSE = 0 mV	5
Input offset current	IIO	-0.07		0.07	nA	VSENSE = 0 mV	5
Gain (A4 devices)	G		200		V/V	A4 devices	5
Gain error	EG	-0.04		1	%	VOUT = 0.1 V to VS, 0.1 V	5
Gain error drift			2	10	ppm/°C	TA = -40°C to +125°C	5
Nonlinearity error		-0.01		0.01	%	VOUT = 0.1 V to VS, 0.1 V	5
Reference voltage rejection ratio	RVRR	-2		10	µV/V	VREF = 100 mV to VS, 100 mV, TA = -40°C to +125°C	5
Maximum capacitive load				1	nF	No sustained oscillation	5
Bandwidth (A4 devices)	BW		33		kHz	A4 devices, CLOAD = 10 pF	5
Slew rate	SR		0.3		V/µs	VS = 5.0 V, VOUT = 0.5 V to 4.5 V	5
Settling time	tS		30		µs	From current step to within 1% of final value	5
Voltage noise density			75		nV/√Hz		5
Leakage input current	IEN		1	100	nA	0 V ≤ VENABLE ≤ VS	5
High-level input voltage (DDF package)	VIH			6	V	DDF Package	5
Low-level input voltage (DDF package)	VIL	0			V	DDF Package	5
Hysteresis (DDF package)	VHYS		300		mV	DDF Package	5
Output leakage disabled	IODIS		1	5	µA	VS = 5.0 V, VOUT = 0 V to 5.0 V, VENABLE = 0 V	5
Quiescent current	IQ		48	65	µA	VS = 1.8 V, VSENSE = 0 mV	5
Quiescent current over temperature	IQ			90	µA	VS = 1.8 V, VSENSE = 0 mV, TA = -40°C to +125°C	5
Quiescent current disabled	IQDIS		10	100	nA	VENABLE = 0 V, VSENSE = 0 mV	6
Supply voltage	VS			6	V		4
Differential input voltage (VIN+), (VIN-)	VIN	-42		42	V		4
Analog inputs with respect to GND	VIN+, VIN-	-0.3		42	V	with respect to GND	4
ENABLE pin voltage	VENABLE	-0.3		6	V		4
Input current into any pin				5	mA		4
Operating temperature	TA	-55		150	°C		4
Junction temperature	TJ			150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Electrostatic discharge, human-body model	V(ESD)	-3000		3000	V	HBM, per ANSI/ESDA/JEDEC JS-001	4
Electrostatic discharge, charged-device model	V(ESD)	-1000		1000	V	CDM, per JEDEC JESD22-C101	4
Common-mode input range	VCM	-0.2		40	V		4
Input pin voltage range	VIN+, VIN-	-0.2		40	V		4
Operating supply voltage	VS	1.7		5.5	V		4
Operating free-air temperature	TA	-40		125	°C		4
Junction-to-ambient thermal resistance (DDF)	RθJA		137.2		°C/W	DDF (SOT23) 8-pin	4
Junction-to-case (top) thermal resistance (DDF)	RθJC(top)		38.4		°C/W	DDF (SOT23) 8-pin	4
Junction-to-board thermal resistance (DDF)	RθJB		57.1		°C/W	DDF (SOT23) 8-pin	4
Junction-to-top characterization parameter (DDF)	ΨJT		5.1		°C/W	DDF (SOT23) 8-pin	4
Junction-to-board characterization parameter (DDF)	ΨJB		56.6		°C/W	DDF (SOT23) 8-pin	4

CAD (KiCad official)

Symbol: INA186A4IDDFR
Footprint: Package_TO_SOT_SMD:TSOT-23-8
3D model: TSOT-23-8 (KiCad packages3D, STEP)
3D model files: ina186a4iddfr-etched.step / ina186a4iddfr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ina186a4iddfr.step / ina186a4iddfr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (45 pp, sha256 9b6f07521db2cf0a, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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INA186A4IDDFR

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