component
DMP6110SSS-13
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDMP6110SSS-13
Diodes Incorporated · MOSFETs · SO-8
DMP6110SSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; the body diode forward current is rated IS = -2.1 A. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; the body diode forward current is rated IS = -2.1 A. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; the body diode forward current is rated IS = -2.1 A. |
| 4 | G | input | Gate terminal; gate-source voltage is rated VGSS = ±20 V. |
| 5 | D | passive | Drain terminal; drain-source voltage is rated VDSS = -60 V with drain current ID = -4.5 A at TA = +25°C (t < 10 s). |
| 6 | D | passive | Drain terminal; drain-source voltage is rated VDSS = -60 V with drain current ID = -4.5 A at TA = +25°C (t < 10 s). |
| 7 | D | passive | Drain terminal; drain-source voltage is rated VDSS = -60 V with drain current ID = -4.5 A at TA = +25°C (t < 10 s). |
| 8 | D | passive | Drain terminal; drain-source voltage is rated VDSS = -60 V with drain current ID = -4.5 A at TA = +25°C (t < 10 s). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -60 | V | VGS = 0V, ID = -250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -48V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = ±16V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(th) | -1 | -3 | V | VDS = VGS, ID = -250µA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 86 | 110 | mΩ | VGS = -10V, ID = -4.5A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 98 | 130 | mΩ | VGS = -4.5V, ID = -3.5A | 2 | |
| Diode Forward Voltage | VSD | -0.7 | -1.2 | V | VGS = 0V, IS = -1A | 2 | |
| Drain-Source Voltage | VDSS | -60 | V | 2 | |||
| Gate-Source Voltage | VGSS | -20 | 20 | V | 2 | ||
| Drain Current | ID | -4.5 | A | VGS = -10V, t < 10s, TA = +25°C | 2 | ||
| Drain Current | ID | -3.6 | A | VGS = -10V, t < 10s, TA = +70°C | 2 | ||
| Maximum Body Diode Forward Current | IS | -2.1 | A | Note 6 | 2 | ||
| Pulsed Drain Current | IDM | -19 | A | 10µs pulse, duty cycle = 1% | 2 | ||
| Avalanche Current | IAS | -17.6 | A | L = 0.1mH (Note 7) | 2 | ||
| Avalanche Energy | EAS | 15.4 | mJ | L = 0.1mH (Note 7) | 2 | ||
| Total Power Dissipation | PD | 1.5 | W | Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Total Power Dissipation | PD | 2 | W | Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Ambient, steady state | RθJA | 80 | °C/W | Note 5, steady state | 2 | ||
| Thermal Resistance, Junction to Ambient, t<10s | RθJA | 48 | °C/W | Note 5, t<10s | 2 | ||
| Thermal Resistance, Junction to Ambient, steady state | RθJA | 61 | °C/W | Note 6, steady state | 2 | ||
| Thermal Resistance, Junction to Ambient, t<10s | RθJA | 37 | °C/W | Note 6, t<10s | 2 | ||
| Thermal Resistance, Junction to Case | RθJC | 6.4 | °C/W | 2 | |||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Body Diode Reverse Recovery Charge Qrr ⎯ 8.8 ⎯ nC IS = -5A, dI/dt = 100A/μs Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. | 2 | |
| contacts | Copper | tin | • Terminals Connections: See Diagram • Terminals: Finish - Matte Tin annealed over Copper lead | 1 |
CAD (KiCad official)
- Symbol:
DMP6110SSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmp6110sss-13-etched.step/dmp6110sss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp6110sss-13.step/dmp6110sss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (6 pp, sha256
5ed13e714be31631, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).