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74HC4017PW

Public Made by Adom

by adom

Nexperia Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC4017PW

Nexperia · Counters, Dividers · TSSOP-16

74HC4017PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q5 output Decoded output Q5, which goes HIGH when the counter is in state 5 and is reset LOW by a HIGH on MR.
2 Q1 output Decoded output Q1, which goes HIGH when the counter is in state 1 and is set LOW by a HIGH on MR.
3 Q0 output Decoded output Q0, which is set HIGH by a HIGH on MR.
4 Q2 output Decoded output Q2, which goes HIGH when the counter is in state 2 and is set LOW by a HIGH on MR.
5 Q6 output Decoded output Q6, which goes HIGH when the counter is in state 6 and is set LOW by a HIGH on MR.
6 Q7 output Decoded output Q7, which goes HIGH when the counter is in state 7 and is set LOW by a HIGH on MR.
7 Q3 output Decoded output Q3, which goes HIGH when the counter is in state 3 and is set LOW by a HIGH on MR.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q8 output Decoded output Q8, which goes HIGH when the counter is in state 8 and is set LOW by a HIGH on MR.
10 Q4 output Decoded output Q4, which goes HIGH when the counter is in state 4 and is set LOW by a HIGH on MR.
11 Q9 output Decoded output Q9, which goes HIGH when the counter is in state 9 and is set LOW by a HIGH on MR.
12 Q5-9 output Carry output, active LOW; it is LOW while the counter is in states 5 to 9 and can drive CP0 of the next counter when cascading.
13 CP1 input Clock input, edge-triggered on a HIGH-to-LOW transition; it advances the counter only while CP0 is HIGH.
14 CP0 input Clock input, edge-triggered on a LOW-to-HIGH transition; it advances the counter only while CP1 is LOW.
15 MR input Master reset input, active HIGH; a HIGH resets the counter to zero independent of the clock inputs.
16 VCC power_in Supply voltage, 2.0 V to 6.0 V for 74HC4017 and 4.5 V to 5.5 V for 74HCT4017 under recommended operating conditions, with an absolute maximum of +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 5
Supply current ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 5
Supply voltage VCC 2 5 6 V 74HC4017 5
Input voltage VI 0 V 5
Output voltage VO 0 V 5
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 5
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 5
Ambient temperature Tamb -40 25 125 °C 5
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 6
HIGH-level output voltage VOH 1.9 2 V IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.9 6 V IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage VOH 3.7 4.32 V IO = -4.0 mA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.2 5.81 V IO = -5.2 mA; VCC = 6.0 V 6
LOW-level output voltage VOL 0 0.1 V IO = 20 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.15 0.4 V IO = 4.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.16 0.4 V IO = 5.2 mA; VCC = 6.0 V 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 6
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 6
Propagation delay CP0 to Qn tpd 63 345 ns CP0 to Qn; CP0 to Q5-9; see Fig. 6; VCC = 2.0 V 8
Propagation delay CP0 to Qn tpd 23 69 ns CP0 to Qn; CP0 to Q5-9; see Fig. 6; VCC = 4.5 V 8
Propagation delay CP0 to Qn tpd 18 59 ns CP0 to Qn; CP0 to Q5-9; see Fig. 6; VCC = 6.0 V 8
Propagation delay CP1 to Qn tpd 61 375 ns CP1 to Qn; CP1 to Q5-9; see Fig. 6; VCC = 2.0 V 8
Propagation delay CP1 to Qn tpd 22 75 ns CP1 to Qn; CP1 to Q5-9; see Fig. 6; VCC = 4.5 V 8
Propagation delay CP1 to Qn tpd 18 64 ns CP1 to Qn; CP1 to Q5-9; see Fig. 6; VCC = 6.0 V 8
HIGH to LOW propagation delay MR to Qn tPHL 52 345 ns MR to Qn; see Fig. 7; VCC = 2.0 V 8
HIGH to LOW propagation delay MR to Qn tPHL 19 69 ns MR to Qn; see Fig. 7; VCC = 4.5 V 8
HIGH to LOW propagation delay MR to Qn tPHL 15 59 ns MR to Qn; see Fig. 7; VCC = 6.0 V 8
LOW to HIGH propagation delay MR to Q5-9, Q0 tPLH 55 345 ns MR to Q5-9, Q0; see Fig. 7; VCC = 2.0 V 8
LOW to HIGH propagation delay MR to Q5-9, Q0 tPLH 20 69 ns MR to Q5-9, Q0; see Fig. 7; VCC = 4.5 V 8
LOW to HIGH propagation delay MR to Q5-9, Q0 tPLH 16 59 ns MR to Q5-9, Q0; see Fig. 7; VCC = 6.0 V 8
Transition time tt 19 110 ns see Fig. 6; VCC = 2.0 V 8
Transition time tt 7 22 ns see Fig. 6; VCC = 4.5 V 8
Transition time tt 6 19 ns see Fig. 6; VCC = 6.0 V 8
Pulse width CP0 and CP1 HIGH or LOW tW 120 17 ns see Fig. 7; VCC = 2.0 V 8
Pulse width CP0 and CP1 HIGH or LOW tW 24 6 ns see Fig. 7; VCC = 4.5 V 8
Pulse width CP0 and CP1 HIGH or LOW tW 20 5 ns see Fig. 7; VCC = 6.0 V 8
Pulse width MR HIGH tW 120 19 ns see Fig. 7; VCC = 2.0 V 8
Pulse width MR HIGH tW 24 7 ns see Fig. 7; VCC = 4.5 V 8
Pulse width MR HIGH tW 20 6 ns see Fig. 7; VCC = 6.0 V 8
Set-up time tsu 75 -8 ns CP1 to CP0; CP0 to CP1; see Fig. 8; VCC = 2.0 V 8
Set-up time tsu 15 -3 ns CP1 to CP0; CP0 to CP1; see Fig. 8; VCC = 4.5 V 8
Set-up time tsu 13 -2 ns CP1 to CP0; CP0 to CP1; see Fig. 8; VCC = 6.0 V 8
Maximum frequency fmax 4 23 MHz CP0 or CP1; see Fig. 7; VCC = 2.0 V 8
Maximum frequency fmax 20 70 MHz CP0 or CP1; see Fig. 7; VCC = 4.5 V 9
Maximum frequency fmax 24 83 MHz CP0 or CP1; see Fig. 7; VCC = 6.0 V 9

CAD (KiCad official)

  • Symbol: 74HC4017PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc4017pw-etched.step / 74hc4017pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4017pw.step / 74hc4017pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 e87046e237160608, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF