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hef4021bt-q100j

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by Ray

Nexperia Shifting Register, SO-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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HEF4021BT-Q100J

Nexperia · Shifting Register · SO-16

HEF4021BT-Q100J from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D7 input Parallel data input bit 7. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS. CMOS logic level referenced to VDD/VSS.
2 Q5 output Buffered parallel output from shift register stage 5. Symmetrical CMOS output driver referenced to VDD/VSS.
3 Q7 output Buffered parallel output from shift register stage 7 (last stage / serial output). Symmetrical CMOS output driver referenced to VDD/VSS.
4 D3 input Parallel data input bit 3. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
5 D2 input Parallel data input bit 2. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
6 D1 input Parallel data input bit 1. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
7 D0 input Parallel data input bit 0. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
8 VSS power_in Ground supply voltage (0 V reference). Tie to system ground.
9 PL input Parallel load input, asynchronous active-HIGH. When PL is HIGH, data on D0-D7 is loaded into the register regardless of CP and DS. When LOW, the register operates in shift mode.
10 CP input Clock input, LOW-to-HIGH edge-triggered. On each rising edge (with PL LOW), data is shifted one position to the right. Schmitt-trigger input tolerant of slow rise/fall times.
11 DS input Serial data input. Shifted into the first register stage on the LOW-to-HIGH transition of CP when PL is LOW.
12 Q6 output Buffered parallel output from shift register stage 6. Symmetrical CMOS output driver referenced to VDD/VSS.
13 D4 input Parallel data input bit 4. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
14 D5 input Parallel data input bit 5. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
15 D6 input Parallel data input bit 6. Asynchronously loaded into the register when PL is HIGH, independent of CP and DS.
16 VDD power_in Positive supply voltage. Recommended operating range 3.0 V to 15.0 V; absolute max 18 V. Bypass to VSS with a local ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-16
Category Logic
Pins 16

Ordering variants

  • HEF4021BT-Q100J
  • HEF4021BT-Q100JHEF4021BTT-Q100

CAD (KiCad official)

  • Symbol: HEF4021BT-Q100J
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (None pp, sha256 4274979b252b739e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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