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AT25SF041B-SSHB-T

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Dialog Semiconductor Adesto Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AT25SF041B-SSHB-T

Dialog Semiconductor Adesto Adesto Technologies · NOR FLASH · SOIC-8

AT25SF041B-SSHB-T from Dialog Semiconductor Adesto Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input CHIP SELECT: asserting CS low selects the device, a high-to-low transition is required to start an operation and a low-to-high transition is required to end it.
2 SO (IO1) bidirectional SERIAL OUTPUT: data is clocked out on the falling edge of SCK, the pin is high-impedance when the device is deselected, and it becomes IO1 in Dual-Output and Quad-Output Read commands.
3 WP (IO2) bidirectional WRITE PROTECT: controls the hardware locking feature, is internally pulled high and can be left floating if hardware protection is not used, and becomes IO2 in Quad commands; connecting it to VCC whenever possible is recommended.
4 GND power_in GROUND: the ground reference for the power supply, to be connected to the system ground.
5 SI (IO0) bidirectional SERIAL INPUT: all command, address and data input is latched on the rising edge of SCK, data is ignored when the device is deselected, and the pin becomes IO0 in Dual-Output and Quad-Output Read commands.
6 SCK input SERIAL CLOCK: command, address and input data on SI are latched on the rising edge of SCK, and output data on SO is clocked out on the falling edge.
7 HOLD (IO3) bidirectional HOLD: temporarily pauses serial communication without deselecting or resetting the device while asserted, is internally pulled high, and becomes IO3 in Quad modes; connecting it to VCC whenever possible is recommended.
8 VCC power_in DEVICE POWER SUPPLY: supplies the source voltage, specified in Section 13.2 as 2.7 V to 3.6 V (or 2.5 V to 3.6 V for the D-grade device).

Key specifications

Parameter Value
Manufacturer Dialog Semiconductor Adesto Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Deep Power-Down Current IDPD 1.2 11 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Standby Current ISB 13.3 30 µA CS, HOLD, WP = VIH; all inputs at CMOS levels 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.3 4.7 mA f = 20 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 3.8 5.4 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (03h, 0Bh) Operation ICC1 4.5 6.5 mA f = 85 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 4.8 6.7 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (3Bh, BBh) Operation (Dual) ICC2 6.2 8.8 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 5.7 8.2 mA f = 50 MHz; IOUT = 0 48
Active Current, Read (6Bh, EBh) Operation (Quad) ICC3 7.6 11.2 mA f = 85 MHz and 108 MHz; IOUT = 0 48
Active Current, Program Operation ICC4 11 18.5 mA CS = VCC 48
Active Current, Erase Operation ICC5 7 12 mA CS = VCC 48
Input Load Current ILI -2 2 µA All inputs at CMOS levels 48
Output Leakage Current ILO -2 2 µA All inputs at CMOS levels 48
Output Low Voltage VOL 0.4 V IOL = 100 µA 48
Operating Temperature (Case), Industrial -40 85 °C 48
VCC Power Supply VCC 2.7 3.6 V 48
Temperature under Bias -55 125 °C 48
Storage Temperature -65 150 °C 48
All Input Voltages (including NC pins) with respect to Ground -0.5 4 V 48
All Output Voltages with respect to Ground -0.6 V Printed upper limit is VCC + 0.5 V 48
Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh, 6Bh fCLK 108 MHz 49
Maximum Clock Frequency for opcodes 0Bh, 3Bh, 6Bh fCLK1 85 MHz 49
Maximum Clock Frequency for 03h opcode fCLK2 55 MHz 49
Clock High Time tCLKH 4 ns 49
Clock Low Time tCLKL 4 ns 49
Clock Rise Time, Peak-to-Peak (Slew Rate) tCLKR 0.1 V/ns 49
Clock Fall Time, Peak-to-Peak (Slew Rate) tCLKF 0.1 V/ns 49
CS High Time tCSH 20 ns 49
CS Low Setup Time (relative to Clock) tCSLS 5 ns 49
CS Low Hold Time (relative to Clock) tCSLH 5 ns 49
CS High Setup Time (relative to Clock) tCSHS 5 ns 49
CS High Hold Time (relative to Clock) tCSHH 5 ns 49
Data In Setup Time tDS 2 ns 49
Data In Hold Time tDH 2 ns 49
Output Disable Time tDIS 6 ns 49
Output Valid Time tV 7 ns 49
Output Hold Time tOH 0 ns 49
HOLD Low Setup Time (relative to Clock) tHLS 5 ns 49
HOLD Low Hold Time (relative to Clock) tHLH 5 ns 49
HOLD High Setup Time (relative to Clock) tHHS 5 ns 49
HOLD High Hold Time (relative to Clock) tHHH 5 ns 49
HOLD Low to Output High-Z tHLQZ 6 ns 49
HOLD High to Output High-Z tHHQZ 6 ns 49
CS High to Standby Mode Without Electronic Signature Read tRES1 20 µs 49
CS High to Standby Mode With Electronic Signature Read tRES2 20 µs 49
CS High to Next Instruction After Suspend tSUS 20 µs 49
Write Protect Setup Time tWPS 20 ns 49
Write Protect Hold Time tWPH 100 ns 49
CS High to Deep Power-Down tEDPD 20 µs 49
CS High to Standby Mode tRDPD 20 µs 49
Resume Deep Power-Down, CS High to ID tRDPO 20 µs 49
Page Program Time (256 Bytes) tPP 0.4 0.8 ms 50
First Byte Program Time tBP1 30 50 µs 50
Second Byte Program Time tBP2 2.5 12 µs 50
Block Erase Time, 4 kbytes tBLKE 60 90 ms 4 kbytes 50
Block Erase Time, 32 kbytes tBLKE 135 210 ms 32 kbytes 50
Block Erase Time, 64 kbytes tBLKE 220 360 ms 64 kbytes 50
Chip Erase Time tCHPE 1.5 3 sec 50
Write Status Register Time tWRSR 5 30 ms 50
Minimum VCC to Chip Select Low Time tVCSL 70 µs 50

CAD (KiCad official)

  • Symbol: AT25SF041B-SSHB-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25sf041b-sshb-t-etched.step / at25sf041b-sshb-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25sf041b-sshb-t.step / at25sf041b-sshb-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Dialog Semiconductor Adesto Adesto Technologies datasheet (58 pp, sha256 330b72d14c016bbd, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF