ATA5279C-WGQW from Microchip Tech, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VS	power_in	Battery supply pin, specified for normal operation from 7 V to 16.5 V and jump start up to 26.5 V.
2	RGND	power_in	Reference ground pin for the internal reference and integrator circuitry.
3	CINT	passive	Integration capacitor connection for the integrator stage.
4	VCC	power_out	Analog 5V stabilization capacitor connection, with internal VCC specified at 4.8 V to 5.3 V in idle mode.
5	VSHS	input	Shunt resistor voltage sense input to the zero cross detector and integrator.
6	VIF	power_in	Digital supply voltage input for the SPI and control interface, with absolute maximum rating of 5.5 V.
7	OSCI	input	Oscillator input pin for the external clock, with frequency range 6.4 MHz to 9.6 MHz.
8	OSCO	output	Oscillator output pin driving the clock network.
9	MACT	output	Modulator active indicator output pin.
10	BCNT	output	LF-bit counter output pin.
11	VSHF1	passive	Shunt resistor driving pin 1 for the return line shunt.
12	A6N1	passive	Coil 6 negative connection line pin 1.
13	A6N2	passive	Coil 6 negative connection line pin 2.
14	A3N1	passive	Coil 3 negative connection line pin 1.
15	A3N2	passive	Coil 3 negative connection line pin 2.
16	A5N1	passive	Coil 5 negative connection line pin 1.
17	A5N2	passive	Coil 5 negative connection line pin 2.
18	VSHF2	passive	Shunt resistor driving pin 2 for the return line shunt.
19	A2N1	passive	Coil 2 negative connection line pin 1.
20	A2N2	passive	Coil 2 negative connection line pin 2.
21	VDS1	power_in	Driver supply pin 1 for the coil driver stages, with VDS operation threshold of 5.1 V to 6 V.
22	A4N1	passive	Coil 4 negative connection line pin 1.
23	A4N2	passive	Coil 4 negative connection line pin 2.
24	A1N1	passive	Coil 1 negative connection line pin 1.
25	A1N2	passive	Coil 1 negative connection line pin 2.
26	A1P	passive	Coil 1 positive connection line pin.
27	VDS2	power_in	Driver supply pin 2 for the coil driver stages.
28	AGND1	power_in	Driver ground pin 1.
29	A4P	passive	Coil 4 positive connection line pin.
30	A2P	passive	Coil 2 positive connection line pin.
31	AGND2	power_in	Driver ground pin 2.
32	A5P	passive	Coil 5 positive connection line pin.
33	A3P	passive	Coil 3 positive connection line pin.
34	A6P	passive	Coil 6 positive connection line pin.
35	AGND3	power_in	Driver ground pin 3.
36	MISO	tri_state	Master-In-Slave-Out SPI output pin, which is tri-state when the chip select is inactive.
37	MOSI	input	Master-Out-Slave-In SPI input pin.
38	S_CS	input	SPI chip select pin; a logic high wakes the chip from power-down mode.
39	S_CLK	input	SPI clock input pin.
40	NRES	input	Chip reset input pin; a negative pulse of at least 100 ns enters power-down mode.
41	IRQ	output	Interrupt request output pin.
42	VDS3	power_in	Driver supply pin 3 for the coil driver stages.
43	PGND1	power_in	Boost converter low-side switch output 1, connected to ground.
44	VL1	input	Boost converter low-side switch input 1.
45	PGND2	power_in	Boost converter low-side switch output 2, connected to ground.
46	VL2	input	Boost converter low-side switch input 2.
47	PGND3	power_in	Boost converter low-side switch output 3, connected to ground.
48	VL3	input	Boost converter low-side switch input 3, with switch overcurrent shutdown level of 2.9 A to 4 A.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	VQFN-48-EP(7x7)
Category	RF & Radio
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Voltage range on pin VS	VVS	-0.3		40	V		28
Voltage range on pins VDSx, VLx	VVDS,max	-0.3		46	V		28
Voltage range on pins AxP	VAxP,max	-0.3			V	max printed as VVDS + 0.3	28
Voltage range on pins VSHFx, VSHS	VVSHF,max	-3			V	max printed as VVCC + 0.3	28
Voltage range on pins AxNx	VAxNx,max			46	V	min printed as VVSHF - 0.3	28
Voltage range on pins VCC, VIF	VDIGSUP,max	-0.3		5.5	V		28
Voltage on pins RGND, PGNDx	VGND,max	-0.3		0.3	V		28
Voltage range on pins NRES, S_CS, S_CLK, MOSI, OSCI, MACT, BCNT, IRQ, MISO, OSCO	VIO,max	-0.3			V	max printed as VVIF + 0.3	28
Voltage range on pin CINT	VCINT,max	-0.3			V	max printed as VVCC + 0.3	28
ESD voltage rating HBM	VESD			2	kV	HBM (MIL-STD-883F, M. 3015.7)	28
Count of peaks over lifetime / peak junction temperature	Tj.max			500000	events	at 200 °C	28
Thermal resistance junction to case	RthJC		10		K/W		28
Thermal resistance junction to ambient	RthJA		35		K/W	value achievable with sufficient thermal vias and heat dissipation area	28
Junction operating temperature range	Tj	-40		145	°C		28
Storage temperature range	Tstg	-40		150	°C		28
VS-pin power-down mode supply current	IVSpd		5.5	10	µA	VVS ≤ 14V	29
VS-pin idle mode supply current	IVS,idle		3.5	5	mA	VVS = 16.5V	29
Internal VCC voltage	VVCC,0, VVCC,1	4.8	5.05	5.3	V	7V ≤ VS ≤ 28V; idle IVCC = 0; load IVCC = 5mA	29
VS voltage clamp at VS = 28V	IVS,C28	50	180	400	µA	VS = 28V	29
VS voltage clamp at VS = 40V	IVS,C40	1.5	3	4.5	mA	VS = 40V	29
VCC power-on reset threshold	VPORVCC	4.1		4.8	V		29
VDS operation threshold	VVDS,min	5.1	5.15	6	V	VS = 16.5V	29
Battery supply range for normal operation	VVS	7		16.5	V	Idle mode	29
VDS power-down mode supply current	IVDS,0	0	0.12	1.4	µA	VVDS = 28V	29
VDS fault-shutdown mode supply current	IVDS,FS		0.85	2.45	mA	VVDS = 16.5V	29
Battery supply range for jump start operation	VVS	7		26.5	V	Idle mode	29
VCC power-up time	tVCC			200	µs		29
Minimum VS voltage level for VCC operation	VVS,min	6			V		29
Overvoltage shutdown level	VVDSmax	40	42	44	V		29
Switch overcurrent shutdown level	IVLmax	2.9	3.2	4	A		29
Max duty cycle (ton / T)	DBoost			0.875			29
Switch leakage current	IVL,leak			500	nA	VVL = 38V	29
Switch fall time	tVL,f		50	200	ns	IVL = 200mA	29
Switch rise time	tVL,r		50	200	ns	IVL = 200mA	29
Minimum data input setup time	tsetup,min	100			ns	Chip in operation	34
Minimum data input hold time	thold,min	100			ns	Chip in operation	34
Output source capability	Vdig,H	4.75			V	VVIF = 5V; ISource = -1mA	34
Output sink capability	Vdig,L			0.25	V	VVIF = 5 V; Isink = 1mA	34
Input current at Vin = 0V	Iin,L	-0.2		0.2	µA	Vin = 0V; VVIF = 5.5V	34
Input high level threshold	VLH	0.48		0.64	VVIF	VVIF = 3.1V	34
Input low level threshold	VHL	0.32		0.48	VVIF	VVIF = 3.1V	34
External reset input timing	tNRES,min	100			ns		34
Tristate output leakage current	IL,max			500	nA	VMISO = 2.5V	34

CAD (KiCad official)

Symbol: ATA5279C-WGQW
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ata5279c-wgqw-etched.step / ata5279c-wgqw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ata5279c-wgqw.step / ata5279c-wgqw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (37 pp, sha256 accba594bf46d502, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ATA5279C-WGQW

Verified ATA5279C-WGQW

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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