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LP38853MRX-ADJ
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP38853MRX-ADJ
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SO-8
LP38853MRX-ADJ from Texas Instruments, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADJ | output | The feedback connection to set the output voltage. |
| 2 | OUT | output | The regulated output voltage. |
| 3 | BIAS | input | The supply for the internal control and reference circuitry. |
| 4 | GND | power_in | Ground. |
| 5 | SS | output | Soft-start capacitor connection. Used to control the rise time of VOUT at turnon. |
| 6 | EN | input | Device enable, High = On, Low = Off. |
| 7 | IN | input | The unregulated voltage input. |
| 8 | N/C | unconnected | No internal connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN supply voltage (survival) | -0.3 | 6 | V | 4 | |||
| VBIAS supply voltage (survival) | -0.3 | 6 | V | 4 | |||
| VSS soft-start voltage (survival) | -0.3 | 6 | V | 4 | |||
| VOUT voltage (survival) | -0.3 | 6 | V | 4 | |||
| Junction temperature | -40 | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| VBIAS supply voltage (survival) | VBIAS | 3 | 5.5 | V | 0.8 V ≤ VOUT ≤ 1.2 V | 4 | |
| VBIAS supply voltage (survival) | VBIAS | 4.5 | 5.5 | V | 1.2 V < VOUT ≤ 1.8 V | 4 | |
| VEN voltage | VEN | 0 | V | maximum is VBIAS | 4 | ||
| IOUT | IOUT | 0 | 3 | mA | 4 | ||
| Junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VADJ accuracy | VADJ | 492.5 | 500 | 507.5 | mV | VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V; 3 V ≤ VBIAS ≤ 5.5 V; 10 mA ≤ IOUT ≤ 3 A; TJ = 25°C | 5 |
| VADJ accuracy | VADJ | 485 | 515 | mV | VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V; 3 V ≤ VBIAS ≤ 5.5 V; 10 mA ≤ IOUT ≤ 3 A | 5 | |
| VADJ accuracy | VADJ | 490 | 500 | 510 | mV | VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS ≤ 4.5 V; 3 V ≤ VBIAS ≤ 5.5 V; 10 mA ≤ IOUT ≤ 3 A; 0°C ≤ TJ ≤ 125°C | 5 |
| VOUT range | VOUT | 0.8 | 1.2 | V | 3 V ≤ VBIAS ≤ 5.5 V | 5 | |
| VOUT range | VOUT | 0.8 | 1.8 | V | 4.5 V ≤ VBIAS ≤ 5.5 V | 5 | |
| Dropout voltage | VDO | 240 | 300 | mV | IOUT = 3 A, TJ = 25°C | 5 | |
| Dropout voltage | VDO | 450 | mV | IOUT = 3 A | 5 | ||
| Quiescent current drawn from VIN supply | IGND(IN) | 7 | 8.5 | mA | VOUT = 0.8 V, VBIAS = 3 V, 10 mA ≤ IOUT ≤ 3 A, TJ = 25°C | 5 | |
| Quiescent current drawn from VIN supply | IGND(IN) | 9 | mA | VOUT = 0.8 V, VBIAS = 3 V, 10 mA ≤ IOUT ≤ 3 A | 5 | ||
| Quiescent current drawn from VIN supply (disabled) | IGND(IN) | 1 | 100 | μA | VEN ≤ 0.5 V, TJ = 25°C | 5 | |
| Quiescent current drawn from VIN supply (disabled) | IGND(IN) | 300 | μA | VEN ≤ 0.5 V | 5 | ||
| Quiescent current drawn from VBIAS supply | IGND(BIAS) | 3 | 3.8 | mA | 10 mA ≤ IOUT ≤ 3 A, TJ = 25°C | 5 | |
| Quiescent current drawn from VBIAS supply | IGND(BIAS) | 4.5 | mA | 10 mA ≤ IOUT ≤ 3 A | 5 | ||
| Quiescent current drawn from VBIAS supply (disabled) | IGND(BIAS) | 100 | 170 | μA | VEN ≤ 0.5 V, TJ = 25°C | 5 | |
| Quiescent current drawn from VBIAS supply (disabled) | IGND(BIAS) | 200 | μA | VEN ≤ 0.5 V | 5 | ||
| Undervoltage lockout threshold | UVLO | 2.2 | 2.45 | 2.7 | V | VBIAS rising until device is functional, TJ = 25°C | 6 |
| Undervoltage lockout threshold | UVLO | 2 | 2.9 | V | VBIAS rising until device is functional | 6 | |
| Undervoltage lockout hysteresis | UVLO(HYS) | 60 | 150 | 300 | mV | VBIAS falling from UVLO threshold until device is non-functional, TJ = 25°C | 6 |
| Undervoltage lockout hysteresis | UVLO(HYS) | 50 | 350 | mV | VBIAS falling from UVLO threshold until device is non-functional | 6 | |
| Soft-start internal resistance | rSS | 11 | 13.5 | 16 | kΩ | 6 | |
| Enable pin current | IEN | -19 | -30 | -40 | μA | VEN = 0 V, VBIAS = 5.5 V, TJ = 25°C | 6 |
| Enable pin current | IEN | -13 | -51 | μA | VEN = 0 V, VBIAS = 5.5 V | 6 | |
| Enable voltage threshold | VEN(ON) | 1 | 1.25 | 1.5 | V | VEN rising until output = ON, TJ = 25°C | 6 |
| Enable voltage threshold | VEN(ON) | 0.9 | 1.55 | V | VEN rising until output = ON | 6 | |
| Enable voltage hysteresis | VEN(HYS) | 50 | 100 | 150 | mV | VEN falling from VEN(ON) until Output = OFF, TJ = 25°C | 6 |
| Enable voltage hysteresis | VEN(HYS) | 30 | 200 | mV | VEN falling from VEN(ON) until Output = OFF | 6 | |
| Turnoff delay time | tOFF | 20 | µs | RLOAD x COUT << tOFF | 6 | ||
| Turnon delay time | tON | 15 | µs | RLOAD x COUT << tON | 6 | ||
| Output short-circuit current | ISC | 5.8 | A | VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, VOUT = 0 V | 6 | ||
| Soft-start time | tSS | 675 | μs | tSS = CSS × rSS × 5; CSS = 10 nF | 6 | ||
| Thermal shutdown junction temperature | TSD | 160 | °C | 6 | |||
| Thermal shutdown hysteresis | TSD(HYS) | 10 | °C | 6 | |||
| Junction-to-ambient thermal resistance | RθJA | 48.4 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 54.6 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 29.1 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 | ||
| Junction-to-top characterization parameter | ψJT | 9.6 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 | ||
| Junction-to-board characterization parameter | ψJB | 29 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.3 | °C/W | DDA (SO PowerPAD) 8-pin package | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. T | 4 | |
| contacts | copper | capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component side, copper surface. The use of vias and long traces to create LDO circuit connections is stron | 19 |
CAD (KiCad official)
- Symbol:
LP38853MRX-ADJ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
lp38853mrx-adj-etched.step/lp38853mrx-adj-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp38853mrx-adj.step/lp38853mrx-adj.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
e20037b18b97e456, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).