component
RT6154AGQW
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Richtek Tech DC-DC Converters, DFN-14-EP(3x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT6154AGQW
Richtek Tech · DC-DC Converters · DFN-14-EP(3x4)
RT6154AGQW from Richtek Tech, in a DFN-14-EP(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VINA | power_in | Supply voltage input, recommended 1.8V to 5.5V, with absolute maximum rating of −0.2V to 6V to GND. |
| 2 | GND | power_in | Analog ground. |
| 3 | FB | input | Voltage feedback of the adjustable version (RT6154A), with a typical regulated value of 500mV; must be connected to VOUT on the fixed 3.3V version (RT6154B). |
| 4 | VOUT | power_out | Buck-boost converter output, adjustable from 1.8V to 5.5V on the RT6154A and fixed at 3.3V on the RT6154B; absolute maximum −0.2V to 6.5V to GND. |
| 5 | VOUT | power_out | Buck-boost converter output (second VOUT pin, same net as pin 4); absolute maximum −0.2V to 6.5V to GND. |
| 6 | LX2 | passive | Second switch node; the buck-boost inductor is connected between LX1 and LX2, with LX2 limited to (PGND − 0.2V) to (PVIN + 0.2V) and 6.5V max. |
| 7 | LX2 | passive | Second switch node (second LX2 pin, same net as pin 6); the inductor is connected between LX1 and LX2. |
| 8 | LX1 | passive | First switch node; the buck-boost inductor is connected between LX1 and LX2, with LX1 limited to (PGND − 0.2V) to (PVIN + 0.2V) and 6V max. |
| 9 | LX1 | passive | First switch node (second LX1 pin, same net as pin 8); the inductor is connected between LX1 and LX2. |
| 10 | VIN | power_in | Power input, recommended 1.8V to 5.5V, with absolute maximum rating of −0.2V to 6V to GND. |
| 11 | VIN | power_in | Power input (second VIN pin, same net as pin 10). |
| 12 | EN | input | Enable control input (1 enabled, 0 disabled) that must not be left open; logic-high minimum 1.2V and logic-low maximum 0.4V. |
| 13 | PS/SYNC | input | Enable/disable control for power save mode (1 disabled, 0 enabled) and clock input for synchronization from 2.2MHz to 2.6MHz; must not be left open. |
| 14 | PGOOD | output | Power good indicator output (1 good, 0 failure), open-drain so it requires a pull-up to the logic supply; low output voltage 0.4V max. |
| 15 | PGND | power_in | Exposed pad, power ground; the exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | DFN-14-EP(3x4) |
| Category | Power Management (PMIC) |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Under-Voltage Lockout Rising Threshold | UVLO_R | 1.6 | 1.7 | 1.8 | V | 5 | |
| Under-Voltage Lockout Falling Threshold | UVLO_F | 1.5 | 1.6 | 1.7 | V | 5 | |
| Minimum Input Voltage for Start-Up | 1.5 | 1.8 | 2 | V | 5 | ||
| FB Voltage | VFB | 0.495 | 0.5 | 0.505 | V | Force PWM (RT6154A) | 5 |
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN = 0V, PS/SYNC = 0V, PGOOD = 0V | 5 | |
| Switching Frequency | fSW | 2.2 | 2.4 | 2.6 | MHz | 5 | |
| Frequency Range for Synchronization | 2.2 | 2.4 | 2.6 | MHz | 5 | ||
| Current Limit | IOC_36 | 3.9 | 5 | 5.8 | A | VIN = VINA = 3.6V | 6 |
| Current Limit | IOC_21 | 1.7 | 2.6 | 3.7 | A | VIN = VINA = 2.1V | 6 |
| Quiescent Current | 20 | 40 | µA | Non switching, EN = VINA, SYNC = 0V | 6 | ||
| Leakage of LX1 and LX2 | ILX1, ILX2 | 5 | µA | All Switch Off | 6 | ||
| EN, PS/SYNC Logic-High Input Voltage | VIH | 1.2 | V | 6 | |||
| EN, PS/SYNC Logic-Low Input Voltage | VIL | 0.4 | V | 6 | |||
| PS/SYNC Input Current | 0.1 | 1 | µA | 6 | |||
| PGOOD Output Low Voltage | 0.04 | 0.4 | V | VOUT = 3.3V, IPGOODL = 10µA | 6 | ||
| PGOOD Output Leakage Current | 0.01 | 0.1 | µA | 6 | |||
| VIN, VINA to GND | -0.2 | 6 | V | 5 | |||
| VOUT to GND | -0.2 | 6.5 | V | 5 | |||
| EN, PS/SYNC to GND | -0.2 | 6 | V | Upper limit printed as (PVIN + 0.2V) with 6V max; 6V cap recorded | 5 | ||
| FB to PGND | -0.2 | 6 | V | Upper limit printed as (PVIN + 0.2V) with 6V max; 6V cap recorded | 5 | ||
| LX1 to PGND | LX1 | -0.2 | 6 | V | Lower limit PGND − 0.2V; upper limit (PVIN + 0.2V) with 6V max; 6V cap recorded | 5 | |
| LX2 to PGND | LX2 | -0.2 | 6.5 | V | Lower limit PGND − 0.2V; upper limit (PVIN + 0.2V) with 6.5V max; 6.5V cap recorded | 5 | |
| LX1, LX2 Switch Node Transient | LX1, LX2 | -3 | 8.5 | V | < 20ns | 5 | |
| Power Dissipation | PD | 3.49 | W | TA = 25°C, WDFN-14AL 4x3 | 5 | ||
| Package Thermal Resistance Junction-to-Ambient | θJA | 28.6 | °C/W | WDFN-14AL 4x3 | 5 | ||
| Package Thermal Resistance Junction-to-Case | θJC | 3.2 | °C/W | WDFN-14AL 4x3 | 5 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec. | 5 | |||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 5 | |||
| Input Voltage Range | VIN | 1.8 | 5.5 | V | 5 | ||
| Output Voltage Range | VOUT | 1.8 | 5.5 | V | 5 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 5 |
CAD (KiCad official)
- Symbol:
RT6154AGQW - Footprint:
Package_DFN_QFN:DFN-14-1EP_3x4mm_P0.5mm_EP1.7x3.3mm - 3D model: DFN-14-EP(3x4) (KiCad packages3D, STEP)
- 3D model files:
rt6154agqw-etched.step/rt6154agqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6154agqw.step/rt6154agqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (15 pp, sha256
d5f60e6ad8ff3176, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).