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SN74AHCT574DBR

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Texas Instruments Flip Flops, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74AHCT574DBR

Texas Instruments · Flip Flops · SSOP-20-208mil

SN74AHCT574DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; when held low, enables output drivers to normal logic state; when held high (≥2 V), forces all outputs to high-impedance state with leakage current ≤2.5 µA.
2 1D input First D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
3 2D input Second D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
4 3D input Third D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
5 4D input Fourth D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
6 5D input Fifth D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
7 6D input Sixth D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
8 7D input Seventh D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
9 8D input Eighth D input; data is sampled on positive edge of clock when OE is low, requiring setup time of 3.5 ns before clock edge and hold time of 1.5 ns after clock edge.
10 GND power_in Ground reference pin; device common return path and circuit reference potential.
11 CLK input Clock input; positive-edge triggered to sample all D inputs into their respective flip-flops with minimum pulse duration of 5.5 ns.
12 8Q tri_state Eighth Q output; outputs the latched data from 8D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
13 7Q tri_state Seventh Q output; outputs the latched data from 7D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
14 6Q tri_state Sixth Q output; outputs the latched data from 6D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
15 5Q tri_state Fifth Q output; outputs the latched data from 5D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
16 4Q tri_state Fourth Q output; outputs the latched data from 4D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
17 3Q tri_state Third Q output; outputs the latched data from 3D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
18 2Q tri_state Second Q output; outputs the latched data from 2D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
19 1Q tri_state First Q output; outputs the latched data from 1D when OE is low, or high-impedance state (≤2.5 µA leakage) when OE is high; maximum source/sink current ±8 mA.
20 VCC power_in Positive power supply pin; operating voltage range 4.5 to 5.5 V with recommended 0.1 µF bypass capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74AHCT574DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74ahct574dbr-etched.step / sn74ahct574dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct574dbr.step / sn74ahct574dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 ac0f8ea4f52711a1, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF