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TS942IDT

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STMicroelectronics Operational Amplifier, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TS942IDT

STMicroelectronics · Operational Amplifier · SO-8

TS942IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Output 1 output Amplifier 1 rail-to-rail output, with 1.5 mA output capability.
2 Inverting Input 1 input Inverting input of amplifier 1 (CMOS input, 1 pA typical bias current).
3 Non-inverting Input 1 input Non-inverting input of amplifier 1 (CMOS input, 1 pA typical bias current).
4 VDD power_in Negative supply or ground; single-supply operation spans VCC of 2.5 V to 10 V relative to VDD.
5 Non-inverting Input 2 input Non-inverting input of amplifier 2 (CMOS input, 1 pA typical bias current).
6 Inverting Input 2 input Inverting input of amplifier 2 (CMOS input, 1 pA typical bias current).
7 Output 2 output Amplifier 2 rail-to-rail output, with 1.5 mA output capability.
8 VCC power_in Positive supply, 2.5 V to 10 V operating with an absolute maximum of 12 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 12 V 2
Storage temperature range Tstg -65 150 °C 2
Maximum junction temperature Tj 150 °C 2
Thermal resistance junction to ambient, SO-8 Rthja 125 °C/W SO-8; typical value per footnote 4 2
Thermal resistance junction to case, SO-8 Rthjc 40 °C/W SO-8; typical value per footnote 4 2
ESD HBM human body model ESD 2 kV HBM 2
ESD MM machine model ESD 200 V MM, TS941 and TS942 2
ESD CDM charged device model ESD 1.5 kV CDM, TS941 - TS944IDT row 2
Latch-up immunity 200 mA 2
Lead temperature (soldering) 250 °C 10 sec 2
Supply voltage VCC 2.5 10 V 3
Operating free air temperature range Toper -40 85 °C 3
Input offset voltage Vio 10 mV VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; TS942 base grade 4
Input offset current Iio 1 100 pA VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 4
Input bias current Iib 1 150 pA VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 4
Common mode rejection ratio CMR 60 85 dB VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 4
Supply voltage rejection ratio SVR 50 78 dB VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 4
Large signal voltage gain Avd 100 dB VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VO = 2 Vpp, RL = 1 MΩ 4
High level output voltage VOH 2.45 2.49 V VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 1 MΩ 4
High level output voltage VOH 2.3 2.4 V VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 10 kΩ 4
Low level output voltage VOL 1 5 mV VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 1 MΩ 4
Low level output voltage VOL 100 200 mV VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 10 kΩ 4
Output source current Io 350 650 µA VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, VO = VDD 4
Output sink current Io 280 500 µA VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, VO = VCC 4
Supply current (per amplifier) ICC 1.2 1.8 µA VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; AVCL = 1, no load 4
Slew rate SR 3 4.5 V/ms VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; RL = 1 MΩ, CL = 50 pF 4
Input offset voltage Vio 10 mV VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; TS942 base grade 5
Input offset current Iio 1 100 pA VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C 5
Input bias current Iib 1 150 pA VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C 5
Common mode rejection ratio CMR 60 85 dB VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C 5
Supply voltage rejection ratio SVR 50 85 dB VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C 5
Large signal voltage gain Avd 100 dB VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VO = 2 Vpp, RL = 1 MΩ 5
High level output voltage VOH 2.9 2.99 V VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 1 MΩ 5
High level output voltage VOH 2.8 2.85 V VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 10 kΩ 5
Low level output voltage VOL 1 5 mV VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 1 MΩ 5
Low level output voltage VOL 100 200 mV VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 10 kΩ 5
Output source current Io 680 1500 µA VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, VO = VDD 5
Output sink current Io 650 1300 µA VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, VO = VCC 5
Supply current (per amplifier) ICC 1.2 1.8 µA VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; AVCL = 1, no load 5
Slew rate SR 3 4.5 V/ms VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C; RL = 1 MΩ, CL = 50 pF 5
Input offset voltage Vio 10 mV VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; TS942 base grade 6
Input offset current Iio 1 100 pA VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 6
Input bias current Iib 1 150 pA VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 6
Common mode rejection ratio CMR 60 85 dB VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 6
Supply voltage rejection ratio SVR 50 85 dB VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 6
Large signal voltage gain Avd 100 dB VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VO = 2 Vpp, RL = 1 MΩ 6
High level output voltage VOH 4.9 4.99 V VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 1 MΩ 6
High level output voltage VOH 4.8 4.85 V VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, RL = 10 kΩ 6
Low level output voltage VOL 1 5 mV VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 1 MΩ 6
Low level output voltage VOL 100 150 mV VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, RL = 10 kΩ 6
Output source current Io 3 4.5 mA VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = 100 mV, VO = VDD 6
Output sink current Io 3.7 5 mA VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; VID = -100 mV, VO = VCC 6
Supply current (per amplifier) ICC 1.2 1.85 µA VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; AVCL = 1, no load 6
Slew rate SR 3 4.5 V/ms VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C; RL = 1 MΩ, CL = 50 pF 6
Input offset voltage drift ΔVio 7 µV/°C VCC=+2.5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 4
Input offset voltage drift ΔVio 7 µV/°C VCC=+3 V, VDD=0 V, RL to VCC/2, Tamb=25°C 5
Input offset voltage drift ΔVio 7 µV/°C VCC=+5 V, VDD=0 V, RL to VCC/2, Tamb=25°C 6

CAD (KiCad official)

  • Symbol: TS942IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: ts942idt-etched.step / ts942idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ts942idt.step / ts942idt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (18 pp, sha256 2a56b163c657899b, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF