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XL2112PBF

Public Made by Adom

by adom

XINLUDA Gate Drivers, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

markdown

XL2112PBF

XINLUDA · Gate Drivers · DIP-14

XL2112PBF from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LO output Low side gate drive output, in phase with LIN and referenced to COM (VLO range 0 to VCC).
2 COM power_in Low side return; all absolute voltage ratings are referenced to COM.
3 VCC power_in Low side fixed supply, recommended 10 to 20V (absolute max 25V), with undervoltage lockout.
4 NC unconnected Position 4 is drawn with no signal name in the 14-lead DIP lead assignment.
5 VS power_in High side floating supply return (offset), operating up to 600V.
6 VB power_in High side floating supply, recommended VS+10V to VS+20V (absolute max 625V), with undervoltage lockout.
7 HO output High side gate drive output, in phase with HIN, swinging between VS and VB.
8 NC unconnected Position 8 is drawn with no signal name in the 14-lead DIP lead assignment.
9 VDD power_in Logic supply, recommended VSS+3V to VSS+20V (absolute max VSS+25V).
10 HIN input Logic input for high side gate driver output (HO), in phase, CMOS Schmitt-triggered with pull-down.
11 SD input Logic input for shutdown, CMOS Schmitt-triggered with pull-down.
12 LIN input Logic input for low side gate driver output (LO), in phase, CMOS Schmitt-triggered with pull-down.
13 VSS power_in Logic ground, with offset of -5V to +5V relative to COM.
14 NC unconnected Position 14 is drawn with no signal name in the 14-lead DIP lead assignment.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Motor Driver ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High Side Floating Supply Voltage VB -0.3 625 V 3
Low Side Fixed Supply Voltage VCC -0.3 25 V 3
Logic Supply Voltage VDD -0.3 V 3
Low Side Output Voltage VLO -0.3 V 3
Allowable Offset Supply Voltage Transient dVs/dt 50 V/ns Figure 2 3
Package Power Dissipation PD 1.6 W TA = +25°C, 14 Lead DIP 3
Thermal Resistance, Junction to Ambient RTHJA 75 °C/W 14 Lead DIP 3
Junction Temperature TJ 150 °C 3
Storage Temperature TS -55 150 °C 3
Lead Temperature (Soldering) TL 300 °C Soldering, 10 seconds 3
High Side Floating Supply Offset Voltage (recommended) VS 600 V Note 1 3
Low Side Fixed Supply Voltage (recommended) VCC 10 20 V 3
Low Side Output Voltage (recommended) VLO 0 V 3
Logic Supply Offset Voltage (recommended) VSS -5 5 V Note 2 3
Ambient Temperature TA -40 85 °C 3
Turn-On Propagation Delay ton 125 180 ns VS = 0V 4
Turn-Off Propagation Delay toff 105 160 ns VS = 600V 4
Shutdown Propagation Delay tsd 105 160 ns VS = 600V 4
Turn-On Rise Time tr 80 130 ns 4
Turn-Off Fall Time tf 40 65 ns 4
Delay Matching, HS & LS Turn-On/Off MT 30 ns 4
Logic '1' Input Voltage VIH 9.5 V 4
Logic '0' Input Voltage VIL 6 V 4
High Level Output Voltage, VBIAS - VO VOH 100 mV IO = 0A 4
Low Level Output Voltage, VO VOL 100 mV IO = 0A 4
Offset Supply Leakage Current ILK 50 µA VB = VS = 600V 4
Quiescent VBS Supply Current IQBS 25 60 µA VIN = 0V or VDD 4
Quiescent VCC Supply Current IQCC 80 180 µA VIN = 0V or VDD 4
Quiescent VDD Supply Current IQDD 2 5 µA VIN = 0V or VDD 4
Logic '1' Input Bias Current IIN+ 20 40 µA VIN = VDD 4
Logic '0' Input Bias Current IIN- 1 µA VIN = 0V 4
VBS Supply Undervoltage Positive Going Threshold VBSUV+ 7.4 8.5 9.6 V 4
VBS Supply Undervoltage Negative Going Threshold VBSUV- 7 8.1 9.2 V 4
VCC Supply Undervoltage Positive Going Threshold VCCUV+ 7.6 8.6 9.6 V 4
VCC Supply Undervoltage Negative Going Threshold VCCUV- 7.2 8.2 9.2 V 4
Output High Short Circuit Pulsed Current IO+ 200 250 mA VO=0V,VIN=VDD, PW 10 µs 4
Output Low Short Circuit Pulsed Current IO- 420 500 mA VO =15V,VIN=0V, PW 10 µs 4

CAD (KiCad official)

  • Symbol: XL2112PBF
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xl2112pbf-etched.step / xl2112pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl2112pbf.step / xl2112pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (15 pp, sha256 9b480d3054ee112d, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF