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CW32F030F6P6

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CW Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CW32F030F6P6

CW · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

CW32F030F6P6 from CW, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PF03/BOOT input Dedicated BOOT pin (I/O structure B) sampled at startup to choose between the internal Bootloader (ISP over UART1 on PA13/PA14) and the user program.
2 PF00 bidirectional GPIO with TC structure whose analog function OSC_IN is the HSE oscillator input for a 4-32 MHz crystal/ceramic resonator (1-32 MHz external clock in bypass mode, VIH min 0.7×VDDIOx).
3 PF01 bidirectional GPIO with TC structure whose analog function OSC_OUT is the HSE oscillator output for a 4-32 MHz crystal/ceramic resonator; the same pin can also carry LSE_OUT for the 32.768 kHz crystal.
4 NRST input Chip reset input with internal pull-up of 7-9 kΩ (8 kΩ typ.); the input must be kept below 0.3×VDD and the reset pulse must be at least 20 µs.
5 VDDA power_in Analog supply 1.65 V to 5.5 V for the ADC, reset circuit, internal RC oscillators and PLL, which must always be greater than or equal to VDD.
6 PA00 bidirectional TTa-structure GPIO used as ADC_IN0 (conversion range 0 to VDDA) and also providing VC1_CH0 and LVD_CH1 analog inputs, with digital alternates UART3_CTS, UART2_CTS, RTC_TAMP, VC1_OUT, SPI2_MISO, GTIM2_CH1 and GTIM2_ETR.
7 PA01 bidirectional TTa-structure GPIO used as ADC_IN1 (0 to VDDA) and VC1_CH1, with digital alternates UART3_RTS, UART2_RTS, I2C2_SCL, LVD_OUT, SPI2_MOSI, GTIM2_CH2 and RTC_TAMP.
8 PA02 bidirectional TTa-structure GPIO used as ADC_IN2 (0 to VDDA) and VC1_CH2, with digital alternates UART3_TXD, UART2_TXD, I2C2_SDA, VC2_OUT, SPI2_SCK, GTIM2_CH3 and AWT_ETR.
9 PA03 bidirectional TTa-structure GPIO used as ADC_IN3 (0 to VDDA) and VC1_CH3, with digital alternates UART3_RXD, UART2_RXD, GTIM2_CH2, PCLK_OUT, SPI2_CS, GTIM2_CH4 and ATIM_CH3A.
10 PA04 bidirectional TTa-structure GPIO used as ADC_IN4 (0 to VDDA) and VC1_CH4, with digital alternates UART2_CTS, I2C2_SCL, HCLK_OUT, SPI1_CS, GTIM2_ETR and ATIM_CH2A.
11 PA05 bidirectional TTa-structure GPIO used as ADC_IN5 (0 to VDDA) and VC1_CH5/VC2_CH0, with digital alternates GTIM2_ETR, UART2_RTS, I2C2_SDA, BTIM2_TOGP, SPI1_SCK, GTIM2_CH1 and ATIM_CH1A.
12 PA06 bidirectional TTa-structure GPIO used as ADC_IN6 (0 to VDDA) and VC1_CH6/VC2_CH1, with digital alternates GTIM3_CH1, UART2_TXD, VC1_OUT, BTIM2_TOGN, SPI1_MISO, GTIM1_CH1 and ATIM_BK.
13 PA07 bidirectional TTa-structure GPIO used as ADC_IN7 (0 to VDDA) and VC1_CH7/VC2_CH2, with digital alternates GTIM4_CH1, UART2_RXD, VC2_OUT, BTIM1_TOGP, SPI1_MOSI, GTIM1_CH2 and ATIM_CH1B.
14 PB01 bidirectional TTa-structure GPIO used as ADC_IN9 (0 to VDDA) and VC2_CH4, with digital alternates UART2_TXD, UART1_RTS, I2C2_SDA, GTIM4_TOGN, BTIM3_TOGP, GTIM1_CH4 and ATIM_CH3B.
15 VSS power_in Ground reference for the digital supply and I/O; all VSS pins must be connected to the same ground.
16 VDD power_in I/O and internal regulator supply 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage.
17 PA09 bidirectional TC-structure GPIO with digital alternates UART3_TXD, UART1_RXD, I2C1_SCL, BTIM1_TOGP, SPI1_CS, GTIM3_CH1 and ATIM_CH2A (no analog function).
18 PA10 bidirectional TC-structure GPIO with digital alternates UART3_RXD, UART1_CTS, I2C1_SDA, BTIM1_TOGN, SPI1_SCK, GTIM3_CH2 and ATIM_CH3A (no analog function).
19 PA13/SWDIO bidirectional TC-structure GPIO that is configured as the SWDIO debug data line after reset with its internal pull-up enabled by default; alternates include I2C1_SDA, UART1_RXD, UART2_RXD, I2C2_SCL and IR_OUT.
20 PA14/SWCLK bidirectional TC-structure GPIO that is configured as the SWCLK debug clock after reset with its internal pull-up enabled by default; alternates include UART3_TXD, I2C1_SCL, UART1_TXD, UART2_TXD and I2C2_SDA.

Key specifications

Parameter Value
Manufacturer CW
Package TSSOP-20
Category Embedded Processors & Controllers
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDD-VSS VDD - VSS -0.3 6 V 34
External analog supply voltage VDDA-VSS VDDA-VSS -0.3 6 V 34
Maximum VDD-VDDA difference when VDD is greater than VDDA VDD-VDDA 0.3 V 34
Sum of currents sunk by all VDD supply lines ΣIVDD 120 mA 34
Sum of currents sourced by all VSS supply lines ΣIVSS -120 mA 34
Sink current of a single VDD supply line IVDD(PIN) 100 mA 34
Source current of a single VSS supply line IVSS(PIN) -100 mA 34
Sink current of a single I/O or control pin IIO(PIN) 25 mA Single I/O or control pin sink current 34
Output current of a single I/O or control pin IIO(PIN) -25 mA Single I/O or control pin output current 34
Sum of sink currents of all I/O or control pins ΣIIO(PIN) 80 mA All I/O or control pins sink total 34
Sum of output currents of all I/O or control pins ΣIIO(PIN) -80 mA All I/O or control pins output total 34
Injection current of TC and RST pins IINJ(PIN) -5 5 mA TC and RST pins 34
Injection current of TTa pins IINJ(PIN) -5 5 mA TTa pins 34
Sum of injection currents of all I/O or control pins ΣIINJ(PIN) -25 25 mA 34
Storage temperature range TSTG -65 150 ℃ 35
Maximum junction temperature TJ 125 ℃ 35
Internal AHB bus frequency fHCLK 0 64 MHz 36
Internal AHB bus frequency at low VDD fHCLK 0 24 MHz VDD < 1.8V 36
Internal APB bus frequency fPCLK 0 64 MHz 36
Internal APB bus frequency at low VDD fPCLK 0 24 MHz VDD < 1.8V 36
Standard operating voltage VDD 1.65 5.5 V 36
Analog operating voltage VDDA 1.65 5.5 V Must equal VDD 36
Ambient temperature (temperature grade 7, maximum power dissipation) TA -40 105 ℃ Temperature grade 7 36
Ambient temperature (low power dissipation) TA -40 125 ℃ Low power dissipation 36
Junction temperature range TJ -40 125 ℃ Temperature grade 7 36
Power dissipation, TSSOP20 package PD 263 mW Temperature grade 7: TA=105℃ 36
VDD rise rate tVDD 0 μs/V 36
VDD fall rate tVDD 20 μs/V 36
VDDA rise rate tVDDA 0 μs/V 36
VDDA fall rate tVDDA 20 μs/V 36
POR/BOR threshold, falling edge VPOR/BOR 1.45 1.5 1.55 V 37
POR/BOR threshold, rising edge VPOR/BOR 1.5 1.55 1.6 V 37
Reset duration tRSTTEMPO 2 2.5 3 ms 37
Internal 1.5V reference voltage VREFINT1V5 1.485 1.5 1.515 V -40℃ < TA < +105℃ 37
Internal 2.5V reference voltage VREFINT2V5 2.475 2.5 2.525 V -40℃ < TA < +105℃ 37
Internal reference voltage distribution over full temperature range ΔVREFINT 10 mV VDDA = 3V 37
Internal reference voltage temperature coefficient TCoeff -60 60 ppm/℃ 37
DeepSleep supply current (regulator in run mode, all oscillators off) IDD 19 40 μA Regulator in run mode, all oscillators off 39
DeepSleep supply current (regulator in run mode, LSI and IWDT on) IDD 20 41 μA Regulator in run mode, LSI and IWDT on 39
Wake-up time from DeepSleep tWUDEEP 4 5 μs Regulator in run mode 41
User external high-speed clock source frequency fHSE_EXT 1 32 MHz 41
OSC_IN input rise/fall time tr(HSE)/tf(HSE) 20 ns 41
HSI factory calibration accuracy ACCHSI -2 2 % TA = -40℃ ~ +105℃ 44
HSI factory calibration accuracy ACCHSI -0.5 0.5 % TA = +25℃ 44
LSI factory calibration accuracy ACCLSI -3 3 % TA = -40℃ ~ +105℃ 44
LSI factory calibration accuracy ACCLSI -1 1 % TA = +25℃ 44
RC10K factory accuracy ACCRC10K -50 50 % TA = -40℃ ~ +105℃ 44
PLL input frequency fPLL_IN 4 24 MHz 45
PLL output frequency fPLL_OUT 8 64 MHz 45
FLASH write mode supply current IDD 3.5 mA 写模式 46
FLASH programming voltage Vprog 1.65 5.5 V 46
FLASH endurance NNED 20000 次 TA = -40℃ ~ +105℃ 46
ESD human body model voltage VESD(HBM) 8 kV TA = +25℃, JESD22-A115C 46
Weak pull-up equivalent resistance (I/O) RPU 50 80 180 kΩ VIN = VSS 47
Weak pull-down equivalent resistance (I/O) RPD 20 30 45 kΩ VIN = VDDIOx 47
High-level output voltage VOH 3.02 V Sourcing 5mA, VDD = 3.3V 48
Low-level output voltage VOL 0.25 V Sinking 6mA, VDD = 3.3V 48
Weak pull-up equivalent resistance (NRST) RPU 7 8 9 kΩ VIN = VSS 50

CAD (KiCad official)

  • Symbol: CW32F030F6P6
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: cw32f030f6p6-etched.step / cw32f030f6p6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32f030f6p6.step / cw32f030f6p6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CW datasheet (72 pp, sha256 a3ae82a897ab1ca3, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF