SN65LVDS9637BDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Supply voltage input, recommended 3 V to 3.6 V (3.3 V nominal), with absolute maximum of -0.5 V to 4 V.
2	1Y	output	Receiver 1 LVTTL output, high for VID >= -32 mV or open input and low for VID <= -100 mV, with VOH of 2.4 V min at -4 mA and VOL of 0.4 V max at 4 mA.
3	2Y	output	Receiver 2 LVTTL output, high for VID >= -32 mV or open input and low for VID <= -100 mV, with VOH of 2.4 V min at -4 mA and VOL of 0.4 V max at 4 mA.
4	GND	power_in	Ground reference for the device.
5	2B	input	Receiver 2 inverting differential input, operating over a -2 V to 4.4 V common-mode voltage range with absolute maximum of -4 V to 6 V.
6	2A	input	Receiver 2 non-inverting differential input, operating over a -2 V to 4.4 V common-mode voltage range with absolute maximum of -4 V to 6 V.
7	1B	input	Receiver 1 inverting differential input, operating over a -2 V to 4.4 V common-mode voltage range with absolute maximum of -4 V to 6 V.
8	1A	input	Receiver 1 non-inverting differential input, operating over a -2 V to 4.4 V common-mode voltage range with absolute maximum of -4 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	3	3.3	3.6	V		5
High-level input voltage, enables	VIH	2			V	Enables	5
Low-level input voltage, enables	VIL			0.8	V	Enables	5
Magnitude of differential input voltage	/VID/	0.1		3	V	LVDS	5
Voltage at any bus terminal (separately or common-mode)	VI or VIC	-2		4.4	V		5
Operating free-air temperature	TA	-40		85	°C		5
Supply voltage range	VCC	-0.5		4	V		5
Voltage range, enables or Y		-0.5			V	max VCC + 3 V	5
Voltage range, A or B		-4		6	V		5
Electrostatic discharge, A and B pins (HBM)				15	kV	Class 3, A pins, MIL-STD-883C Method 3015.7	5
Electrostatic discharge, B pins (HBM)				600	V	Class 3, B pins, MIL-STD-883C Method 3015.7	5
Storage temperature range		-65		150	°C		5
Lead temperature				260	°C	1,6 mm (1/16 inch) from case for 10 seconds	5
Power rating, D8 package				725	mW	TA ≤ 25°C	5
Operating factor, D8 package			5.8		mW/°C	Above TA = 25°C	5
Power rating, D8 package				377	mW	TA = 85°C	5
Positive-going differential input voltage threshold	VIT1			50	mV	IB = -2 V or 4.4 V, See Figure 1 and Figure 2	6
Negative-going differential input voltage threshold	VIT2	-50			mV	IB = -2 V or 4.4 V, See Figure 1 and Figure 2	6
Differential input fail-safe voltage threshold	VIT3	-100		-32	mV	See Table 1 and Figure 5	6
Differential input voltage hysteresis, VIT1 - VIT2	VID(HYS)	50			mV		6
High-level output voltage	VOH	2.4			V	IOH = -4 mA	6
Low-level output voltage	VOL			0.4	V	IOL = 4 mA	6
Supply current, '9637B	ICC		8	12	mA	No load, Steady-state	6
Input current (A or B inputs), SN65LVDS	II	-20		20	µA	VI = 0 V, Other input open	6
Input current (A or B inputs), SN65LVDS	II	-40		40	µA	VI = -2 V, Other input open	6
Differential input current, SN65LVDS	ID	-3		3	µA	VID = 100 mV, VIC = -2 V or 4.4 V, See Figure 1	6
Power-off input current (A or B inputs), SN65LVDS	I(OFF)	-20		20	µA	VA or VB = 0 V or 2.4 V, VCC = 0 V	6
Power-off input current (A or B inputs), SN65LVDS	I(OFF)	-35		35	µA	VA or VB = -2 V or 4.4 V, VCC = 0 V	6
High-impedance output current	IOZ	-10		10	µA		6
Input capacitance, A or B input to GND	CI		5		pF	VI = 0.4 sin (4E6πt) + 0.5 V	6
Propagation delay time, low-to-high-level output	tPLH	2.5	4	6	ns	See Figure 3	7
Propagation delay time, high-to-low-level output	tPHL	2.5	4	6	ns	See Figure 3	7
Delay time, fail-safe deactivate time	td1			9	ns	See Figure 3 and Figure 6	7
Delay time, fail-safe activate time	td2		0.3	1.5	µs		7
Pulse skew (/tPHL1 - tPLH1/)	tsk(p)			200	ps		7
Output skew	tsk(o)			150	ps		7
Part-to-part skew	tsk(pp)			1	ns	CL = 10 pF, See Figure 3	7
Output signal rise time	tr			0.8	ns		7
Output signal fall time	tf			0.8	ns		7
Propagation delay time, high-level-to-high-impedance output	tPHZ		5.5	9	ns	See Figure 4	7
Propagation delay time, low-level-to-high-impedance output	tPLZ		4.4	9	ns	See Figure 4	7
Propagation delay time, high-impedance-to-high-level output	tPZH		3.8	9	ns	See Figure 4	7
Propagation delay time, high-impedance-to-low-level output	tPZL		7	9	ns	See Figure 4	7

CAD (KiCad official)

Symbol: SN65LVDS9637BDR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: sn65lvds9637bdr-etched.step / sn65lvds9637bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds9637bdr.step / sn65lvds9637bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (23 pp, sha256 a6fe6aaf7a83af37, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65LVDS9637BDR

Verified SN65LVDS9637BDR

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3D Model

Symbol & Footprint

Schematic Symbol

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