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BQ76942PFBR

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Texas Instruments Battery Management, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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BQ76942PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ76942PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected This pin is not connected to silicon.
2 VC9 input Ninth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC8.
3 NC unconnected This pin is not connected to silicon.
4 VC8 input Eighth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC7.
5 NC unconnected This pin is not connected to silicon.
6 VC7 input Seventh cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC6.
7 NC unconnected This pin is not connected to silicon.
8 VC6 input Sixth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC5.
9 NC unconnected This pin is not connected to silicon.
10 VC5 input Fifth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC4.
11 NC unconnected This pin is not connected to silicon.
12 VC4 input Fourth cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC3.
13 VC3 input Third cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC2.
14 VC2 input Second cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC1.
15 VC1 input First cell sense voltage input, VSS-0.3 to VSS+85 V relative to VC0.
16 VC0 input First cell negative terminal voltage input, VSS-0.3 to VSS+6 V.
17 VSS power_in Device ground connection.
18 SRP input Coulomb counter sense resistor top input, VSS-0.3 to VREG18 + 0.3 V during operation.
19 NC unconnected This pin is not connected to silicon.
20 SRN input Coulomb counter sense resistor bottom input, VSS-0.3 to VREG18 + 0.3 V during operation.
21 TS1 bidirectional Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V.
22 TS2 bidirectional Thermistor or ADC input and SHUTDOWN mode wakeup pin, accepting VSS-0.2 to VREG18 + 0.3 V, with weak pulldown to VSS in SHUTDOWN.
23 TS3 bidirectional Thermistor or general purpose ADC input, accepting VSS-0.2 to VREG18 + 0.3 V.
24 REG18 power_out Internal 1.8 V LDO output regulated to 1.6 to 2.0 V, providing 3 to 14 mA short-circuit current limit for internal use.
25 ALERT bidirectional Multifunction pin for alarm interrupt, HDQ interface, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
26 SCL bidirectional I2C clock or SPI serial clock with open-drain output, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode.
27 SDA bidirectional I2C data or SPI MISO with open-drain for I2C or active drive for SPI, VSS-0.3 to VSS+6 V, supporting 400 kHz I2C mode.
28 HDQ bidirectional Multifunction pin for HDQ single-wire, SPI MOSI, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
29 CFETOFF bidirectional Charge FET disable input (low disables CHG/PCHG), SPI chip select, thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
30 DFETOFF bidirectional Discharge FET disable input (low disables DSG/PDSG or both in BOTHOFF mode), thermistor, or digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
31 DCHG bidirectional Charge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
32 DDSG bidirectional Discharge FET fault status open-drain output or thermistor/digital I/O (VSS-0.3 to VSS+6 V, or VSS-0.2 to VREG18 + 0.3 V for ADC/thermistor).
33 RST_SHUT input Reset or shutdown digital input, VSS-0.3 to VSS+6 V logic level, with >1 second assertion triggering SHUTDOWN mode.
34 REG2 power_out Second programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit.
35 REG1 power_out First programmable LDO output (1.8 V / 2.5 V / 3.0 V / 3.3 V / 5.0 V selectable), providing up to 45 mA with 47 to 80 mA short-circuit current limit.
36 REGIN input LDO supply input providing ~5.5 V from internal pre-regulator or external source for REG1 and REG2, with voltage range maximum of VSS-0.3 or VBREG-5.5 to minimum of VSS+6 or VBAT+0.3.
37 BREG output Pre-regulator base drive for external NPN BJT, maximum output current 2.5 to 3.33 mA at short circuit.
38 FUSE bidirectional Fuse drive output (VSS-0.3 to minimum of VSS+20 or VBAT+0.3 V) and secondary protector sense input (VSS-0.3 to VSS+6 V with maximum 2 mA current limit).
39 PDSG output Predischarge PFET gate control output, voltage approximately VBAT to VBAT-0.5 V depending on supply level.
40 PCHG output Precharge PFET gate control output, voltage approximately VPACK to VPACK-0.5 V depending on supply level.
41 LD bidirectional Load detect pin for pack removal sensing (VSS-0.3 to VSS+85 V) or current source output in SHUTDOWN mode, with internal pullup current 35 to 172 µA.
42 PACK input PACK+ voltage sense input measuring top-of-stack after protection FETs, VSS-0.3 to VSS+85 V, with ±0.5 V measurement accuracy after calibration.
43 DSG output Discharge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT.
44 NC unconnected This pin is not connected to silicon.
45 CHG output Charge NFET gate drive output, VSS-0.3 to VSS+85 V range, gate-source voltage 4.5 to 7 V (low overdrive) or 10 to 13 V (high overdrive) relative to BAT.
46 CP1 bidirectional Charge pump external capacitor connection (100 to 2200 nF recommended), voltage range VBAT-0.3 to minimum of VSS+85 or VBAT+15 V.
47 BAT power_in Primary power supply input from battery stack top through series diode, VSS-0.3 to VSS+85 V absolute maximum, typical 4.7 to 55 V operating range.
48 VC10 input Tenth cell top-of-stack sense voltage input, measuring between maximum of VSS-0.3 and VC9-0.3 to VSS+85 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ76942PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq76942pfbr-etched.step / bq76942pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq76942pfbr.step / bq76942pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 a976a88e92abb957, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF