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TPH1R405PL

Public Made by Adom

by adom

TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPH1R405PL

TOSHIBA · MOSFETs · SOP-8

TPH1R405PL from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Source passive Source terminal of the N-channel MOSFET; pins 1, 2 and 3 are all designated Source.
2 Source passive Source terminal of the N-channel MOSFET; pins 1, 2 and 3 are all designated Source.
3 Source passive Source terminal of the N-channel MOSFET; pins 1, 2 and 3 are all designated Source.
4 Gate input Gate terminal of the N-channel MOSFET, which operates in enhancement mode with Vth of 1.4 to 2.4 V (VDS = 10 V, ID = 0.5 mA).
5 Drain passive Drain terminal of the N-channel MOSFET; pins 5, 6, 7 and 8 are all designated Drain.
6 Drain passive Drain terminal of the N-channel MOSFET; pins 5, 6, 7 and 8 are all designated Drain.
7 Drain passive Drain terminal of the N-channel MOSFET; pins 5, 6, 7 and 8 are all designated Drain.
8 Drain passive Drain terminal of the N-channel MOSFET; pins 5, 6, 7 and 8 are all designated Drain.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDSS 45 V 2
Gate-source voltage VGSS -20 20 V 2
Drain current (DC), silicon limit ID 232 A Tc = 25 (Silicon limit) 2
Drain current (DC), package limited ID 120 A Note 1, Note 2 (limited 120 A by package capability) 2
Drain current (pulsed) IDP 500 A t = 100 µs 2
Single-pulse avalanche energy EAS 114 mJ Note 5: VDD = 36 V, Tch = 25 (initial), L = 6.1 µH, IAS = 120 A 2
Single-pulse avalanche current IAS 120 A Note 5: VDD = 36 V, Tch = 25 (initial), L = 6.1 µH 2
Channel temperature Tch 175 °C 2
Storage temperature Tstg -55 175 °C 2
Channel-to-case thermal resistance Rth(ch-c) 1.13 /W Tc = 25 2
Channel-to-ambient thermal resistance Rth(ch-a) 50 /W Ta = 25, Note 3: glass-epoxy board (a) 2
Channel-to-ambient thermal resistance Rth(ch-a) 156 /W Ta = 25, Note 4: glass-epoxy board (b) 2
Gate leakage current IGSS -0.1 0.1 µA VGS = ±20 V, VDS = 0 V 3
Drain cut-off current IDSS 10 µA VDS = 45 V, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSS 45 V ID = 10 mA, VGS = 0 V 3
Drain-source breakdown voltage (VGS = -20 V mode) V(BR)DSX 30 V ID = 10 mA, VGS = -20 V 3
Gate threshold voltage Vth 1.4 2.4 V VDS = 10 V, ID = 0.5 mA 3
Drain-source on-resistance RDS(ON) 1.61 2.3 mΩ VGS = 4.5 V, ID = 50 A 3
Drain-source on-resistance RDS(ON) 1.4 mΩ VGS = 10 V, ID = 50 A 3
Input capacitance Ciss 4830 6300 pF VDS = 22.5 V, VGS = 0 V, f = 1 MHz 3
Reverse transfer capacitance Crss 66 122 pF VDS = 22.5 V, VGS = 0 V, f = 1 MHz 3
Gate resistance rg 0.37 Ω 3
Output capacitance Coss 1210 pF VDS = 22.5 V, VGS = 0 V, f = 1 MHz 3
Switching time (rise time) 11 ns See Fig. 6.2.1; VDD ≈ 22.5 V, VGS = 0 V/10 V, ID = 50 A, RL = 0.45 Ω, RGG = 4.7 Ω, RGS = 4.7 Ω 3
Switching time (turn-on time) ton 27 ns See Fig. 6.2.1; VDD ≈ 22.5 V, VGS = 0 V/10 V, ID = 50 A, RL = 0.45 Ω, RGG = 4.7 Ω, RGS = 4.7 Ω 3
Switching time (fall time) tf 21 ns See Fig. 6.2.1; VDD ≈ 22.5 V, VGS = 0 V/10 V, ID = 50 A, RL = 0.45 Ω, RGG = 4.7 Ω, RGS = 4.7 Ω 3
Switching time (turn-off time) toff 70 ns See Fig. 6.2.1; VDD ≈ 22.5 V, VGS = 0 V/10 V, ID = 50 A, RL = 0.45 Ω, RGG = 4.7 Ω, RGS = 4.7 Ω 3
Total gate charge (gate-source plus gate-drain) Qg 74 nC VDD ≈ 22.5 V, VGS = 10 V, ID = 50 A 3
Gate-drain charge Qgd 18 nC VDD ≈ 22.5 V, VGS = 10 V, ID = 50 A 3
Gate switch charge QSW 22 nC 3
Output charge Qoss 67 nC VDS = 22.5 V, VGS = 0 V, f = 1 MHz 3
Reverse drain current (pulsed) IDRP 500 A t = 100 µs 4
Diode forward voltage VDSF -1.2 V IDR = 120 A, VGS = 0 V 4
Reverse recovery time trr 49 ns VR = 22.5 V, IDR = 30 A, VGS = 0 V, -dIDR/dt = 100 A/µs 4
Reverse recovery charge Qrr 54 nC VR = 22.5 V, IDR = 30 A, VGS = 0 V, -dIDR/dt = 100 A/µs 4

CAD (KiCad official)

  • Symbol: TPH1R405PL
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tph1r405pl-etched.step / tph1r405pl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tph1r405pl.step / tph1r405pl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 fc12749214a3a728, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF