component
LP4435T1G
Public Made by Adomby adom
LRC MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLP4435T1G
LRC · MOSFETs · SOP-8
LP4435T1G from LRC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with pins 2 and 3; continuous source (diode) current is limited to -2.1 A. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 3; continuous source (diode) current is limited to -2.1 A. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with pins 1 and 2; continuous source (diode) current is limited to -2.1 A. |
| 4 | G | input | Gate of the P-channel MOSFET, with gate-source voltage limited to ±20 V and threshold VGS(th) of -1 V at ID = -250 uA. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 6-8; VDS max -30 V, continuous ID -9.5 A at TA=25°C, pulsed -38 A. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 7 and 8; VDS max -30 V, continuous ID -9.5 A at TA=25°C, pulsed -38 A. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5, 6 and 8; VDS max -30 V, continuous ID -9.5 A at TA=25°C, pulsed -38 A. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied internally with pins 5-7; VDS max -30 V, continuous ID -9.5 A at TA=25°C, pulsed -38 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -30 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current | ID | -9.5 | A | TA=25°C | 1 | ||
| Continuous Drain Current | ID | -7 | A | TA=70°C | 1 | ||
| Pulsed Drain Current | IDM | -38 | A | 1 | |||
| Continuous Source Current (Diode Conduction) | IS | -2.1 | A | 1 | |||
| Power Dissipation | PD | 3.1 | W | TA=25°C | 1 | ||
| Power Dissipation | PD | 2.2 | W | TA=70°C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Gate-Source Threshold Voltage | VGS(th) | -1 | -1.6 | -3 | V | VDS = VGS, ID = -250 uA | 2 |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ±20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | -1 | uA | VDS = -24 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -10 | uA | VDS = -24 V, VGS = 0 V, TJ = 55°C | 2 | ||
| On-State Drain Current | ID(on) | -20 | A | VDS = -5 V, VGS = -10 V | 2 | ||
| Drain-Source On-Resistance | rDS(on) | 24 | mΩ | VGS = -10 V, ID = -7 A | 2 | ||
| Drain-Source On-Resistance | rDS(on) | 37 | mΩ | VGS = -4.5 V, ID = -5 A | 2 | ||
| Diode Forward Voltage | VSD | -1.5 | V | IS = -1 A, VGS = 0 V | 2 | ||
| Maximum Junction-to-Ambient (t <= 10 sec) | RθJA | 40 | °C/W | t <= 10 sec | 2 | ||
| Maximum Junction-to-Ambient (Steady State) | RθJA | 80 | °C/W | Steady State | 2 |
CAD (KiCad official)
- Symbol:
LP4435T1G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
lp4435t1g-etched.step/lp4435t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lp4435t1g.step/lp4435t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (5 pp, sha256
7619142488b0ee17, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).