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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS1294IPAG

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS1294IPAG from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN8N	input	Differential analog negative input 8, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
2	IN8P	input	Differential analog positive input 8, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
3	IN7N	input	Differential analog negative input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
4	IN7P	input	Differential analog positive input 7, used only on ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
5	IN6N	input	Differential analog negative input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
6	IN6P	input	Differential analog positive input 6, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
7	IN5N	input	Differential analog negative input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
8	IN5P	input	Differential analog positive input 5, used on ADS1296 and ADS1298; tie to AVDD if unused, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
9	IN4N	input	Differential analog negative input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
10	IN4P	input	Differential analog positive input 4; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
11	IN3N	input	Differential analog negative input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
12	IN3P	input	Differential analog positive input 3; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
13	IN2N	input	Differential analog negative input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
14	IN2P	input	Differential analog positive input 2; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
15	IN1N	input	Differential analog negative input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
16	IN1P	input	Differential analog positive input 1; full-scale differential input is ±VREF/gain, and analog inputs must stay between AVSS - 0.3 V and AVDD + 0.3 V.
17	TESTP_PACE_OUT1	bidirectional	Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used.
18	TESTN_PACE_OUT2	bidirectional	Internal test signal or single-ended buffered output for pace detection, selected by register settings; can also serve as an auxiliary differential input when hardware pace detection is not used.
19	AVDD	power_in	Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors.
20	AVSS	power_in	Analog ground, the reference for AVDD and the internal reference generation.
21	AVDD	power_in	Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors.
22	AVDD	power_in	Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors.
23	AVSS	power_in	Analog ground, the reference for AVDD and the internal reference generation.
24	VREFP	bidirectional	Positive reference input/output; the reference is VREFP - VREFN, which is 2.5 V on a 3 V supply or 4 V on a 5 V supply, and VREFP must be between AVSS and AVSS + 2.5 V.
25	VREFN	input	Negative reference input; it must be connected to AVSS when the internal reference is used.
26	VCAP4	passive	Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
27	NC	unconnected	No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor.
28	VCAP1	passive	Analog bypass capacitor node; connect a 22 µF capacitor to AVSS.
29	NC	unconnected	No connect; may be tied to AVDD or AVSS through a 10 kΩ resistor.
30	VCAP2	passive	Analog bypass capacitor node; connect a 1 µF capacitor to AVSS.
31	RESV1	input	Reserved for future use; must be connected to logic low (DGND).
32	AVSS	power_in	Analog ground, the reference for AVDD and the internal reference generation.
33	DGND	power_in	Digital ground.
34	DIN	input	SPI data input; it is latched on the falling edge of SCLK.
35	PWDN	input	Power-down input, active low; pulling it low powers down all on-chip circuits.
36	RESET	input	System reset input, active low; hold low for the minimum pulse width before releasing it.
37	CLK	bidirectional	External master clock input or internal oscillator clock output; the external clock is 2.048 MHz nominal (1.94 MHz to 2.25 MHz) when CLKSEL = 0.
38	START	input	Start conversion input; the digital input must stay within DGND to DVDD.
39	CS	input	SPI chip select, active low; it must stay low for the full serial transaction.
40	SCLK	input	SPI serial clock input, with Schmitt-trigger input; it should be kept free of noise.
41	DAISY_IN	input	Daisy-chain input; tie to DGND when not used.
42	GPIO1	bidirectional	General-purpose digital I/O pin 1; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused).
43	DOUT	output	SPI data output; data is shifted out on the rising edge of SCLK, and the pin goes high impedance when CS is high.
44	GPIO2	bidirectional	General-purpose digital I/O pin 2; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused).
45	GPIO3	bidirectional	General-purpose digital I/O pin 3; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused).
46	GPIO4	bidirectional	General-purpose digital I/O pin 4; configured as input or output by the GPIO register, and must be driven when used as an input (tie to DGND if unused).
47	DRDY	output	Data ready output, active low; it goes low when new conversion data is available.
48	DVDD	power_in	Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors.
49	DGND	power_in	Digital ground.
50	DVDD	power_in	Digital supply; DVDD must be 1.65 V to 3.6 V and it should be decoupled with 1 µF and 0.1 µF capacitors.
51	DGND	power_in	Digital ground.
52	CLKSEL	input	Master clock select; low selects the external clock on CLK, high selects the internal oscillator.
53	AVSS1	power_in	Analog ground for the charge pump; connect it in a star configuration to AVSS.
54	AVDD1	power_in	Analog supply for the charge pump, which has transients at fCLK; connect it in a star configuration to AVDD.
55	VCAP3	passive	Internally generated AVDD + 1.9 V node; connect a 1 µF capacitor to AVSS.
56	AVDD	power_in	Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors.
57	AVSS	power_in	Analog ground, the reference for AVDD and the internal reference generation.
58	AVSS	power_in	Analog ground, the reference for AVDD and the internal reference generation.
59	AVDD	power_in	Analog supply; AVDD - AVSS must be 2.7 V to 5.25 V and it should be decoupled with 1 µF and 0.1 µF ceramic capacitors.
60	RLDREF	input	Right-leg drive non-inverting input, used as the RLD reference voltage.
61	RLDINV	bidirectional	Right-leg drive inverting input; it connects to the RLD amplifier feedback network.
62	RLDIN	input	Multiplexer input for the right-leg drive signal; tie it to the channel mux per the datasheet configuration (tie to AVDD if unused).
63	RLDOUT	output	Right-leg drive amplifier output, which drives the patient through the external feedback network.
64	WCT	output	Wilson central terminal output; its drive is limited, so it must be buffered before driving low-impedance loads and it is intended for very high input impedance (typically above 500 MΩ).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS1294IPAG
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads1294ipag-etched.step / ads1294ipag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1294ipag.step / ads1294ipag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (113 pp, sha256 a8830f56bfd11d1b, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF