component
DS8572-12S5
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDS8572-12S5
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
DS8572-12S5 from DSTECH, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply voltage with a recommended operating range of 2.3V to 6V; place a 1µF or larger input capacitor close to the VIN and GND pins. |
| 2 | GND | power_in | Ground pin; the input and output capacitor ground connections must return to this pin using as wide and as short a copper trace as is practical. |
| 3 | EN | input | Enable control input with a rising threshold VIH of 1.0V and a falling threshold VIL of 0.4V; pulling it low puts the regulator in shutdown with a typical shutdown current of 0.1µA. |
| 4 | NC | unconnected | No internal connection. |
| 5 | VOUT | power_out | Output of the regulator, rated for up to 600mA with current limit of 950mA typical; output capacitor must meet a minimum 1mΩ ESR and 1µF to 22µF effective capacitance and be placed close to VOUT and GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | 2.3 | 6 | V | 7 | ||
| DC Output Voltage Accuracy | -2 | 2 | % | ILOAD = 0.1mA | 7 | ||
| Dropout Voltage (VOUT = 1.2V) | VDROP_1.2V | 0.15 | V | ILOAD = 100mA; VOUT = 1.2V | 7 | ||
| Ground Current | IQ | 30 | μA | ILOAD = 0mA | 7 | ||
| Shutdown Ground Current | ISD | 0.1 | 0.5 | μA | VEN = 0V, VOUT = 0V | 7 | |
| Enable Threshold Voltage (rising) | VIH | 1 | V | EN Rising | 7 | ||
| Enable Threshold Voltage (falling) | VIL | 0.4 | V | EN Falling | 7 | ||
| EN Input Current | IEN | 10 | 100 | nA | VEN = 5V | 7 | |
| Line Regulation | ΔLINE | 15 | mV | ILOAD = 30mA, 2.5V ≤ VIN ≤ 5.5V or (VOUT + 0.2V) ≤ VIN ≤ 5.5V | 7 | ||
| Load Line | ΔLOAD | 20 | mV | 1mA ≤ ILOAD ≤ 300mA | 7 | ||
| Output Current Limit | ILIM | 601 | 950 | mA | VOUT = 0V | 7 | |
| Thermal Shutdown Temperature | TSD | 160 | °C | ILOAD = 10mA | 7 | ||
| Thermal Shutdown Hysteresis | ΔTSD | 20 | °C | 7 | |||
| Discharge Resistance | RDC | 30 | Ω | EN = 0V, VOUT = 0.1V | 7 | ||
| Input/Enable to GND voltage | VIN, EN | -0.3 | 7 | V | to GND | 6 | |
| Output to GND voltage | VOUT | -0.3 | 6 | V | to GND | 6 | |
| Output to input voltage | VOUT - VIN | -6 | 0.3 | V | to VIN | 6 | |
| Lead Temperature (soldering, 10 sec) | 260 | °C | Soldering, 10 sec | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Storage Temperature Range | -60 | 150 | °C | 6 | |||
| ESD HBM | HBM | 2 | kV | 6 | |||
| ESD MM | MM | 200 | V | 6 | |||
| ESD CDM | CDM | 2 | kV | 6 | |||
| Input Voltage (recommended) | VIN | 2.3 | 6 | V | 6 | ||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | °C | 6 | ||
| Ambient Temperature Range (recommended) | TA | -40 | 85 | °C | 6 | ||
| Thermal Resistance, junction to ambient (SOT-23-5) | θJA | 220 | °C/W | TA = 25°C, DSTECH EVB board (Note 2) | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | must be back to the DS8572 ground pin using as wide and as short of a copper trace as is practical. | 12 |
CAD (KiCad official)
- Symbol:
DS8572-12S5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
ds8572-12s5-etched.step/ds8572-12s5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8572-12s5.step/ds8572-12s5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (16 pp, sha256
465072f372f9b049, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).