component
NSI8141N1
Public Made by Adomby adom
NOVOSENSE Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownNSI8141N1
NOVOSENSE · Digital Isolators · SOIC-16
NSI8141N1 from NOVOSENSE, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for isolator side 1, specified at 2.5 V to 5.5 V in the recommended operating conditions, with a 0.1 µF bypass capacitor to GND1 placed as close to the package as possible. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | INA | input | Logic input A; the datasheet specifies VIH minimum 2 V and VIL maximum 0.8 V. |
| 4 | INB | input | Logic input B; the datasheet specifies VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | INC | input | Logic input C; the datasheet specifies VIH minimum 2 V and VIL maximum 0.8 V. |
| 6 | OUTD | output | Logic output D; the datasheet specifies VOH of VDD-0.3 V at IOH = -4 mA and VOL of 0.3 V at IOL = 4 mA. |
| 7 | NC/ EN1 | input | No connection, or output enable 1: an active-high input where EN1 high or NC enables the side 1 outputs and EN1 low disables them to high impedance. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | EN2 | input | Output enable 2: an active-high input where EN2 high or NC enables the side 2 outputs and EN2 low disables them to high impedance. |
| 11 | IND | input | Logic input D; the datasheet specifies VIH minimum 2 V and VIL maximum 0.8 V. |
| 12 | OUTC | output | Logic output C; the datasheet specifies VOH of VDD-0.3 V at IOH = -4 mA and VOL of 0.3 V at IOL = 4 mA. |
| 13 | OUTB | output | Logic output B; the datasheet specifies VOH of VDD-0.3 V at IOH = -4 mA and VOL of 0.3 V at IOL = 4 mA. |
| 14 | OUTA | output | Logic output A; the datasheet specifies VOH of VDD-0.3 V at IOH = -4 mA and VOL of 0.3 V at IOL = 4 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Power supply for isolator side 2, specified at 2.5 V to 5.5 V in the recommended operating conditions, with a 0.1 µF bypass capacitor to GND2 placed as close to the package as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VDD1, VDD2 | 2.5 | 5.5 | V | 4 | ||
| Operating Temperature | Topr | -40 | 125 | ℃ | 4 | ||
| Power Supply Voltage | VDD1, VDD2 | -0.5 | 6.5 | V | 3 | ||
| Maximum Input Voltage | VINA, VINB, VINC, VIND | -0.4 | V | 3 | |||
| Maximum Output Voltage | VOUTA, VOUTB, VOUTC | -0.4 | V | 3 | |||
| Maximum Input/Output Pulse Voltage | VINA, VINB, VINC, VOUTA, VOUTB, VOUTC | -0.8 | V | Pulse width should be less than 100ns, and the duty cycle should be less than 10% | 3 | ||
| Output current | Io | -15 | 15 | mA | 3 | ||
| Maximum Surge Isolation Voltage | VIOSM | 5.3 | kV | 3 | |||
| Operating Temperature | Topr | -40 | 125 | ℃ | 3 | ||
| Storage Temperature | Tstg | -40 | 150 | ℃ | 3 | ||
| Electrostatic discharge HBM | HBM | -6000 | 6000 | V | 3 | ||
| Electrostatic discharge CDM | CDM | -2000 | 2000 | V | 3 | ||
| Common-Mode Transients | CMTI | -150 | 150 | kV/us | 3 | ||
| Input Pull high or low Current | Ipull | 8 | 15 | uA | 4 | ||
| Common Mode Transient Immunity | CMTI | 100 | 150 | kV/us | 4 | ||
| Supply current NSi8141 IDD1(Q0) | IDD1(Q0) | 1.244 | 1.87 | mA | All Input at supply for NSi8141x1; VDD1=5V±10% | 5 | |
| Supply current NSi8141 IDD2(Q0) | IDD2(Q0) | 2.164 | 3.25 | mA | All Input at supply for NSi8141x1; VDD2=5V±10% | 5 | |
| Supply current NSi8141 IDD1(Q1) | IDD1(Q1) | 4.658 | 7 | mA | All Input 0V for NSi8141x1; VDD1=5V±10% | 5 | |
| Supply current NSi8141 IDD2(Q1) | IDD2(Q1) | 3.416 | 5 | mA | All Input 0V for NSi8141x1; VDD2=5V±10% | 5 | |
| Supply current NSi8141 IDD1(1M) | IDD1(1M) | 3.07 | 4.6 | mA | All Input with 1Mbps, CL=15pF | 5 | |
| Supply current NSi8141 IDD2(1M) | IDD2(1M) | 3.064 | 4.6 | mA | All Input with 1Mbps, CL=15pF | 5 | |
| Supply current NSi8141 IDD1(10M) | IDD1(10M) | 3.82 | 5.7 | mA | All Input with 10Mbps, CL=15pF | 5 | |
| Supply current NSi8141 IDD2(10M) | IDD2(10M) | 5.496 | 8.2 | mA | All Input with 10Mbps, CL=15pF | 5 | |
| Supply current NSi8141 IDD1(100M) | IDD1(100M) | 10.708 | 16.06 | mA | All Input with 100Mbps, CL = 15pF | 5 | |
| Supply current NSi8141 IDD2(100M) | IDD2(100M) | 29.336 | 44 | mA | All Input with 100Mbps, CL = 15pF | 5 | |
| Data Rate | DR | 0 | 150 | Mbps | 6 | ||
| Propagation Delay | tPLH | 5 | 8.2 | 15 | ns | See Figure 2.9, CL = 15pF | 6 |
| Propagation Delay | tPHL | 5 | 10.56 | 15 | ns | See Figure 2.9, CL = 15pF | 6 |
| Power on Reset | VDDPOR | 2.2 | V | POR threshold as during power-up | 4 | ||
| POR threshold Hysteresis | VDD HYS | 0.1 | V | POR threshold Hysteresis | 4 | ||
| Input Threshold | VIT | 1.6 | V | Input Threshold at rising edge | 4 | ||
| Input Threshold Hysteresis | VIT_HYS | 0.4 | V | Input Threshold Hysteresis | 4 | ||
| High Level Input Voltage | VIH | 2 | V | 4 | |||
| Low Level Input Voltage | VIL | 0.8 | V | 4 | |||
| Low Level Output Voltage | VOL | 0.3 | V | IOL = 4mA | 4 | ||
| Output Impedance | Rout | 50 | ohm | 4 | |||
| Start Up Time after POR | trbs | 40 | usec | 4 | |||
| Minimum Pulse Width | PW | 5 | ns | 6 | |||
| Pulse Width Distortion | PWD | 5 | ns | See Figure 2.9, CL = 15pF | 6 | ||
| Rising Time | tr | 5 | ns | See Figure 2.9, CL = 15pF | 6 | ||
| Falling Time | tf | 5 | ns | See Figure 2.9, CL = 15pF | 6 | ||
| Peak Eye Diagram Jitter | tJIT(PK) | 350 | ps | 6 | |||
| Channel-to-Channel Delay Skew | tSK(c2c) | 2.5 | ns | 6 | |||
| Part-to-Part Delay Skew | tSK(p2p) | 5 | ns | 6 | |||
| Disable high to Tri-State | tPHZ | 14.88 | ns | See Figure 2.10, CL = 15pF, RL=1k | 6 | ||
| Enable to Data high Valid | tPZH | 10 | ns | See Figure 2.10, CL = 15pF, RL=1k | 6 | ||
| Disable low to Tri-State | tPLZ | 17.25 | ns | See Figure 2.10, CL = 15pF, RL=1k | 6 | ||
| Enable to Data high Valid | tPZL | 10.85 | ns | See Figure 2.10, CL = 15pF, RL=1k | 6 | ||
| High Level Input Voltage (recommended) | VIH | 2 | V | 4 | |||
| Low Level Input Voltage (recommended) | VIL | 0.8 | V | 4 | |||
| Data rate (recommended) | DR | 150 | Mbps | 4 | |||
| Junction-to-Air Thermal Resistance (NB-SOIC-16) | θJA | 78.9 | °C/W | NB-SOIC-16 column | 4 | ||
| Junction-to-case (top) thermal resistance (NB-SOIC-16) | θJC(top) | 41.1 | °C/W | NB-SOIC-16 column | 4 | ||
| Junction-to-board thermal resistance (NB-SOIC-16) | θJB | 49.5 | °C/W | NB-SOIC-16 column | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN VDE V 0884-11, each NSi8140N/NSi8141N/NSi8142N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec (partial discharge detection limit = 5 pC). The * ma | 14 |
CAD (KiCad official)
- Symbol:
NSI8141N1 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
nsi8141n1-etched.step/nsi8141n1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsi8141n1.step/nsi8141n1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (24 pp, sha256
7b822401bb111f58, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).