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Contents

README

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TL084AP

Sungine · FET Input Amplifiers · SOP-14

TL084AP from Sungine, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Output1 output Output of amplifier 1.
2 IN1- input Inverting input of amplifier 1.
3 IN1+ input Non-inverting input of amplifier 1.
4 Vcc power_in Positive supply, absolute maximum +18 V.
5 IN2+ input Non-inverting input of amplifier 2.
6 IN2- input Inverting input of amplifier 2.
7 Output2 output Output of amplifier 2.
8 Output3 output Output of amplifier 3.
9 IN3- input Inverting input of amplifier 3.
10 IN3+ input Non-inverting input of amplifier 3.
11 VEE power_in Negative supply, absolute maximum -18 V.
12 IN4+ input Non-inverting input of amplifier 4.
13 IN4- input Inverting input of amplifier 4.
14 Output4 output Output of amplifier 4.

Key specifications

Parameter Value
Manufacturer Sungine
Package SOP-14
Category Amplifiers/Comparators
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 5 15 mV RS≤10K, VCM=0V, VCC=+15V, VEE=-15V, TA=25℃ 3
Input offset current IIO 5 200 pA VCM=0V, TA=25℃ 3
Input bias current IIB 30 400 pA VCM=0V, TA=25℃ 3
Common-mode input voltage range VICR 10 V min printed as ±10; typ printed '15,-12'; TA=25℃ 3
Large signal voltage gain AVOL 25 150 V/mV VO=±10V, RL≥2.0K, TA=25℃ 3
Output voltage swing (peak-to-peak) VO 24 28 V RL=10K, TA=25℃ 3
Common-mode rejection ratio CMRR 70 100 dB RS≤10K, TA=25℃ 3
Power supply rejection ratio PSRR 70 100 dB RS≤10K, TA=25℃ 3
Supply current (per amplifier) ID 1.4 2.8 mA TA=25℃ 3
Supply voltage VCC VCC 18 V 2
Supply voltage VEE VEE -18 V 2
Differential input voltage VID -30 30 V 2
Input voltage range VIDR -15 15 V Note 1: must not exceed supply voltage 2
Power dissipation PD 680 mW plastic DIP package, derate above TA=+47℃ at 10 mW/℃ 2
Temperature range (printed as solder junction temperature) TA 0 70 ℃ 2
Storage temperature range TSTG -65 150 ℃ 2
Input offset voltage VIO 20 mV RS≤10K, VCM=0V, TA=0℃~70℃, VCC=+15V, VEE=-15V 2
Input offset current IIO 5 nA VCM=0V, TA=0℃~70℃ 2
Input bias current IIB 10 nA VCM=0V, TA=0℃~70℃ 2
Large signal voltage gain AVOL 15 V/mV VO=±10V, RL≥2.0K, TA=0℃~70℃ 2
Output voltage swing (peak-to-peak) VO 24 V RL≥10K, TA=0℃~70℃ 2
Output voltage swing (peak-to-peak) VO 20 V RL≥2.0K, TA=0℃~70℃ 2
Average temperature coefficient of input offset voltage ∆VIO/∆T 10 uV/℃ RS=50, TA=0℃~70℃ 3
Input impedance RJ 1012 TA=25℃ 3
Unity-gain bandwidth BW 4 MHz TA=25℃ 3
Slew rate SR 13 V/us VIN=10V, RL=2.0K, CL=100pF 3
Rise time TR 0.1 us see Figure 1 3
Overshoot OS 10 % VIN=20mV, RL=2.0K, CL=100pF 3
Equivalent input noise voltage EN 25 nV√Hz RS=100, f=1.0KHz 3
Channel separation CS 120 dB AV=100 3

CAD (KiCad official)

  • Symbol: TL084AP
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: tl084ap-etched.step / tl084ap-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl084ap.step / tl084ap.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (8 pp, sha256 975e643e5b5c46f7, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF