Turns one upstream USB port into three downstream ports, in a USB 2.0 full-speed hub. It handles the hub enumeration and per-port connect and power logic itself, with PWRON/OVRCUR pins for each port to switch and monitor downstream power, and a ganged or per-port power mode. It runs bus-powered or self-powered and takes an optional external EEPROM for custom descriptors. A simple, self-contained way to fan out a full-speed USB port.

Pinout

Pin	Name	Type	Function
1	DP0	bidirectional	Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port (full-speed, 12 Mb/s).
2	DM0	bidirectional	Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
3	VCC	power_in	3.3-V supply voltage (recommended 3.0-3.6 V).
4	RESET	input	Active-low TTL reset input with hysteresis. Must be asserted at power up; recommended pulse width 100 μs-1 ms after VCC reaches 90%. Clock must be active during the last 60 μs of the reset window.
5	EECLK	output	EEPROM serial clock. When EXTMEM is low, EECLK acts as a 3-state serial clock output to the EEPROM with a 100-μA internal pulldown. When EXTMEM is high the EEPROM interface is disabled and this pin must be left floating.
6	EEDATA/GANGED	bidirectional	Muxed EEPROM serial data / power-management mode indicator. When EXTMEM is low it is the serial data I/O for the EEPROM (100-μA internal pulldown). When EXTMEM is high it selects ganged vs. per-port overcurrent detection for the downstream ports; TTL input that must not change dynamically during operation.
7	GND	power_in	Ground reference. Must be tied to ground for proper operation.
8	BUSPWR	input	Active-low power-source indicator. Pull low for bus-powered mode or to 3.3 V for self-powered mode. Must not change dynamically during operation.
9	PWRON1	output	Active-low push-pull power-on/off control for downstream port 1. Drives external 5-V power switch device; output cannot drive 5-V signals so the switch must accept 3.3-V logic inputs.
10	OVRCUR1	input	Active-low overcurrent input for downstream port 1. Sampled every 2 ms with noise-filter logic (valid on two consecutive samples).
11	DM1	bidirectional	USB downstream port 1 differential data minus.
12	DP1	bidirectional	USB downstream port 1 differential data plus.
13	PWRON2	output	Active-low push-pull power-on/off control for downstream port 2. Drives external 5-V power switch device (3.3-V compatible input required).
14	OVRCUR2	input	Active-low overcurrent input for downstream port 2. Noise-filtered (sampled every 2 ms).
15	DM2	bidirectional	USB downstream port 2 differential data minus.
16	DP2	bidirectional	USB downstream port 2 differential data plus.
17	PWRON3	output	Active-low push-pull power-on/off control for downstream port 3. Drives external 5-V power switch device (3.3-V compatible input required).
18	OVRCUR3	input	Active-low overcurrent input for downstream port 3. Noise-filtered; has an internal pull-up that can be enabled for 2-port operation.
19	DM3	bidirectional	USB downstream port 3 differential data minus.
20	DP3	bidirectional	USB downstream port 3 differential data plus.
21	OCPROT/PWRSW	input	Dual-function active-low input. On a bus-powered hub (BUSPWR=GND) this is the overcurrent-protection implementation indicator (OCPROT); on a self-powered hub (BUSPWR=VCC) it is the power-switching implementation indicator (PWRSW). Logic high disables the internal pulldown.
22	NPINT0	input	Number of ports internal to hub system (permanently attached), bit 0. See Table 1 in datasheet.
23	NPINT1	input	Number of ports internal to hub system (permanently attached), bit 1. See Table 1 in datasheet.
24	NP3	input	Active-low port-count select. Logic 0 configures the hub for 3 downstream ports; logic 1 configures for 2 downstream ports.
25	VCC	power_in	3.3-V supply voltage (recommended 3.0-3.6 V).
26	EXTMEM	input	External-EEPROM enable. When high, the serial EEPROM interface is disabled and default VID/PID are used. When low, pins 5 and 6 act as the EEPROM clock and data pins.
27	DP0PUR	output	DP0 pullup-resistor enable. Floats (inactive) for ~15 ms after RESET or after any change on BUSPWR, then drives to VCC (3.3 V) until the next reset or BUSPWR change. Enables onboard bus/self-power dynamic switching.
28	GND	power_in	Ground reference. Must be tied to ground for proper operation.
29	XTAL2	output	6-MHz crystal output. Leave open when using an external oscillator/clock source.
30	XTAL1/CLK48	input	Muxed crystal / 48-MHz clock input. When MODE is low, this is a 6-MHz crystal input (50% duty cycle) driving an internal APLL that generates the 48-MHz and 12-MHz core clocks. When MODE is high, this pin is driven by a 48-MHz external clock and the APLL is bypassed.
31	MODE	input	Clock-source mode select. Low = APLL output clock (6-MHz crystal or oscillator on XTAL1); high = XTAL1/CLK48 driven directly by a 48-MHz clock source.
32	SUSPND	output	Suspend-status output. Active-high; asserted high during USB suspend to allow external logic to power down. Low during normal operation.

Key specifications

Parameter	Value
Type	USB 2.0 full-speed hub
Ports	1 upstream, 3 downstream
Power	Bus- or self-powered
Port power	Ganged or per-port (PWRON / OVRCUR)
Descriptors	Internal or external EEPROM
Supply	3.3 V
Package	LQFP-32

Ordering variants

Same part, different packaging or reel option.

TUSB2036VF (LQFP-32)
TUSB2036IVF (LQFP-32, industrial)
TUSB2036IPT (LQFP-32)

CAD (KiCad official)

Symbol: Interface_USB:TUSB2036 (KiCad official)
Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
3D model: LQFP-32 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (29 pp, sha256 66da8c4b2e0dd932, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF