component

SN74F573DWR

Public Made by Adom

by adom

Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74f573dwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74F573DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74F573DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered active-low output enable: when low the eight Q outputs show their normal logic states, and when high they are forced to the high-impedance state without affecting the latch contents.
2 1D input Data input to latch 1; while LE is high the 1Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
3 2D input Data input to latch 2; while LE is high the 2Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
4 3D input Data input to latch 3; while LE is high the 3Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
5 4D input Data input to latch 4; while LE is high the 4Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
6 5D input Data input to latch 5; while LE is high the 5Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
7 6D input Data input to latch 6; while LE is high the 6Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
8 7D input Data input to latch 7; while LE is high the 7Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
9 8D input Data input to latch 8; while LE is high the 8Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling).
10 GND power_in Ground reference pin for the device.
11 LE input Latch enable input shared by all eight latches: while high the Q outputs are transparent to D, and taking it low latches the Q outputs (minimum high pulse width 6 ns).
12 8Q tri_state Latch 8 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
13 7Q tri_state Latch 7 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
14 6Q tri_state Latch 6 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
15 5Q tri_state Latch 5 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
16 4Q tri_state Latch 4 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
17 3Q tri_state Latch 3 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
18 2Q tri_state Latch 2 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
19 1Q tri_state Latch 1 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA).
20 VCC power_in Positive supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V) for the SN74F573.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74F573DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74f573dwr-etched.step / sn74f573dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f573dwr.step / sn74f573dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (13 pp, sha256 3e8c5339d5889276, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF