CY8C4125PVI-482T from Cypress Semicon, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1.0	bidirectional	Port 1 Pin 0: GPIO, LCD, CSD, CTB (ctb.oa0.inp) and PWM (tcpwm2_p[1]).
2	P1.1	bidirectional	Port 1 Pin 1: GPIO, LCD, CSD, CTB (ctb.oa0.inm) and PWM (tcpwm2_n[1]).
3	P1.2	bidirectional	Port 1 Pin 2: GPIO, LCD, CSD, CTB (ctb.oa0.out) and PWM (tcpwm3_p[1]).
4	P1.7/VREF	bidirectional	Port 1 Pin 7: GPIO, LCD, CSD, CTB (ctb.oa1.inp_alt) and optional external SAR reference input/bypass (ext_vref).
5	P2.2	bidirectional	Port 2 Pin 2: GPIO, LCD, CSD, SARMUX input (sarmux.2).
6	P2.3	bidirectional	Port 2 Pin 3: GPIO, LCD, CSD, SARMUX input (sarmux.3).
7	P2.4	bidirectional	Port 2 Pin 4: GPIO, LCD, CSD, SARMUX input (sarmux.4) and PWM (tcpwm0_p[1]).
8	P2.5	bidirectional	Port 2 Pin 5: GPIO, LCD, CSD, SARMUX input (sarmux.5) and PWM (tcpwm0_n[1]).
9	P2.6	bidirectional	Port 2 Pin 6: GPIO, LCD, CSD, SARMUX input (sarmux.6) and PWM (tcpwm1_p[1]).
10	P2.7	bidirectional	Port 2 Pin 7: GPIO, LCD, CSD, SARMUX input (sarmux.7) and PWM (tcpwm1_n[1]).
11	P3.0	bidirectional	Port 3 Pin 0: GPIO, LCD, CSD, PWM (tcpwm0_p[0]) and SCB1 UART RX / I2C SCL / SPI MOSI.
12	P3.1	bidirectional	Port 3 Pin 1: GPIO, LCD, CSD, PWM (tcpwm0_n[0]) and SCB1 UART TX / I2C SDA / SPI MISO.
13	P3.2	bidirectional	Port 3 Pin 2: GPIO, LCD, CSD, PWM (tcpwm1_p[0]), SCB1 SPI clock and SWD I/O (swd_io[0]), which is an SWD pin after boot (reset).
14	P3.3	bidirectional	Port 3 Pin 3: GPIO, LCD, CSD, PWM (tcpwm1_n[0]), SCB1 SPI SSEL0 and SWD clock (swd_clk[0]), which is an SWD pin after boot (reset).
15	P4.0	bidirectional	Port 4 Pin 0: GPIO, LCD, CSD and SCB0 UART RX / I2C SCL / SPI MOSI.
16	P4.1	bidirectional	Port 4 Pin 1: GPIO, LCD, CSD and SCB0 UART TX / I2C SDA / SPI MISO.
17	P4.2	bidirectional	Port 4 Pin 2: GPIO, LCD, CSD (csd_c_mod) and SCB0 SPI clock.
18	P4.3	bidirectional	Port 4 Pin 3: GPIO, LCD, CSD (csd_c_sh_tank) and SCB0 SPI SSEL0.
19	P0.0	bidirectional	Port 0 Pin 0: GPIO, LCD, CSD, comparator 1 positive input (comp1_inp) and SCB0 SPI SSEL1.
20	P0.1	bidirectional	Port 0 Pin 1: GPIO, LCD, CSD, comparator 1 negative input (comp1_inn) and SCB0 SPI SSEL2.
21	P0.2	bidirectional	Port 0 Pin 2: GPIO, LCD, CSD, comparator 2 positive input (comp2_inp) and SCB0 SPI SSEL3.
22	P0.3	bidirectional	Port 0 Pin 3: GPIO, LCD, CSD and comparator 2 negative input (comp2_inn).
23	P0.6	bidirectional	Port 0 Pin 6: GPIO, LCD, CSD, external clock input (ext_clk) and SCB1 SPI clock.
24	P0.7	bidirectional	Port 0 Pin 7: GPIO, LCD, CSD, wakeup and SCB1 SPI SSEL0.
25	XRES	input	Chip reset, active low; has an internal pull-up resistor that is always enabled.
26	VCCD	power_out	Regulated digital supply (1.8 V ±5%); connect to a 1 µF capacitor (1 µF to 1.6 µF, X5R or better) or to 1.8 V.
27	VDD	power_in	Supply pin shared as VDDD and VDDA on this package, 1.8 - 5.5 V.
28	VSS	power_in	Ground pin, shared as VSSA on this package.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	SSOP-28-208mil
Category	Embedded Processors & Controllers
Pins	28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Digital supply relative to VSSD	VDDD_ABS	-0.5		6	V	Absolute max	19
Direct digital core voltage input relative to Vssd	VCCD_ABS	-0.5		1.95	V	Absolute max	19
GPIO voltage	VGPIO_ABS	-0.5		6	V	Absolute max; printed as VDD+0.5	19
Maximum current per GPIO	IGPIO_ABS	-25		25	mA	Absolute max	19
GPIO injection current	IGPIO_injection	-0.5		0.5	mA	Absolute max, current injected per pin	19
ESD human body model	ESD_HBM	2200			V		19
ESD charged device model	ESD_CDM	500			V		19
Pin current for latch-up	LU	-200		200	mA		19
Power supply input voltage (VDDA = VDDD = VDD)	VDD	1.8		5.5	V	With regulator enabled	19
Power supply input voltage unregulated	VDDD	1.71	1.8	1.89	V	Internally unregulated supply	19
Output voltage (for core logic)	VCCD		1.8		V		19
External regulator voltage (VCCD) bypass	CEFC	1	1.3	1.6	µF	X5R ceramic or better	19
Power supply decoupling capacitor	CEXC		1		µF	X5R ceramic or better	19
Active current, 6 MHz	IDD4			2.8	mA	Execute from Flash; CPU at 6 MHz; VDD = 1.71 V to 5.5 V	19
Active current, 6 MHz	IDD5		2.2		mA	Execute from Flash; CPU at 6 MHz; T = 25 °C	19
Active current, 12 MHz	IDD7			4.2	mA	Execute from Flash; CPU at 12 MHz	19
Active current, 12 MHz	IDD8		3.7		mA	Execute from Flash; CPU at 12 MHz; T = 25 °C	19
Active current, 24 MHz	IDD11		6.7		mA	Execute from Flash; CPU at 24 MHz; T = 25 °C	19
Active current, 24 MHz	IDD12			7.2	mA	Execute from Flash; CPU at 24 MHz	19
Sleep current, 6 MHz	IDD20		1.3	1.8	mA	I2C wakeup, WDT, and Comparators on. 6 MHz; VDD = 1.71 to 5.5 V	19
Sleep current, 12 MHz	IDD20A		1.7	2.2	mA	I2C wakeup, WDT, and Comparators on. 12 MHz; VDD = 1.71 to 5.5 V	19
Deep Sleep current, 1.8-3.6 V	IDD27			45	µA	I2C wakeup and WDT on; T = 85 °C	20
Deep Sleep current, 3.6-5.5 V	IDD29		1.5	15	µA	I2C wakeup and WDT on; Typ at 25 °C, Max at 85 °C	20
Deep Sleep current, regulator bypassed	IDD33			60	µA	I2C wakeup and WDT on; T = 85 °C	20
Hibernate current, 1.8-3.6 V	IDD36			1000	nA	GPIO and Reset active; T = 85 °C	20
Hibernate current, regulator bypassed	IDD42			1000	nA	GPIO and Reset active; T = 85 °C	20
Stop Mode current	IDD43A		20	80	nA	VDD = 3.3 V; Typ at 25 °C, Max at 85 °C	20
Supply current while XRES asserted	IDD_XR		2	5	mA		20
CPU frequency	FCPU	0		24	MHz	1.71 ≤ VDD ≤ 5.5; printed min DC	20
Wakeup from sleep mode	TSLEEP		0		µs	Guaranteed by characterization	20
Wakeup from Deep Sleep mode	TDEEPSLEEP			25	µs	24-MHz IMO. Guaranteed by characterization	20
Wakeup from Hibernate and Stop modes	THIBERNATE			2	ms	Guaranteed by characterization	20
External reset pulse width	TRESETWIDTH	1			µs	Guaranteed by characterization	20
Trimmed internal reference to SAR	VREFSAR	-1		1	%	Percentage of Vbg (1.024 V). Guaranteed by characterization	33
Clock switching from clk1 to clk2	TCLKSWITCH	3		4	Periods	In clk1 periods. Guaranteed by design	33
Number of wait states at 24 MHz	TWS24	0				CPU execution from Flash. Guaranteed by characterization	33
Operating ambient temperature	TA	-40	25	105	°C		36
Operating junction temperature	TJ	-40		125	°C		36
Package thermal resistance junction-to-ambient (28-pin SSOP)	TJA		66.58		°C/Watt		36
Package thermal resistance junction-to-case (28-pin SSOP)	TJC		26.28		°C/Watt		36
Solder reflow peak temperature (28-pin SSOP)				260	°C	Maximum time at peak 30 seconds	36

CAD (KiCad official)

Symbol: CY8C4125PVI-482T
Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
3D model: SSOP-28-208mil (KiCad packages3D, STEP)
3D model files: cy8c4125pvi-482t-etched.step / cy8c4125pvi-482t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4125pvi-482t.step / cy8c4125pvi-482t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (44 pp, sha256 96f5358c3c46932a, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY8C4125PVI-482T

Verified CY8C4125PVI-482T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README