component
74HC573S
Public Made by Adomby adom
GR Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC573S
GR · Latches · SOIC-20-300mil
74HC573S from GR, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ~{OE} | input | Active-low output enable: when high, all Q outputs go to high impedance (Z); when low, the outputs operate as push-pull. |
| 2 | 1D | input | Data input 1; Q1 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 3 | 2D | input | Data input 2; Q2 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 4 | 3D | input | Data input 3; Q3 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 5 | 4D | input | Data input 4; Q4 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 6 | 5D | input | Data input 5; Q5 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 7 | 6D | input | Data input 6; Q6 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 8 | 7D | input | Data input 7; Q7 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 9 | 8D | input | Data input 8; Q8 follows this input while LE is high and holds its value when LE goes low. Input voltage limit is -0.5 V to VCC+0.5 V. |
| 10 | GND | power_in | Ground reference (0 V) for the device; the datasheet specifies the device ground pin for the 2 V to 6 V supply. |
| 11 | LE | input | Latch enable: when high, the outputs follow D; when low, the outputs are latched and ignore D. Minimum LE high pulse width is 80 ns at VCC=2 V, 20 ns at 4.5 V and 15 ns at 6 V. |
| 12 | 8Q | tri_state | Three-state output 8, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 13 | 7Q | tri_state | Three-state output 7, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 14 | 6Q | tri_state | Three-state output 6, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 15 | 5Q | tri_state | Three-state output 5, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 16 | 4Q | tri_state | Three-state output 4, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 17 | 3Q | tri_state | Three-state output 3, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 18 | 2Q | tri_state | Three-state output 2, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 19 | 1Q | tri_state | Three-state output 1, able to drive the bus directly or up to 15 LSTTL loads; high impedance when OE is high. |
| 20 | VCC | power_in | Positive supply; recommended operating range is 2.0 V to 6.0 V (absolute maximum 6.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6.5 | V | 2 | ||
| Input/output voltage | VIN、VOUT | -0.5 | V | 2 | |||
| Input/output clamp current | IIK、IOK | 20 | mA | 2 | |||
| Continuous output current per pin | IOUT | 35 | mA | 2 | |||
| Continuous current through VCC or GND | ICC、IGND | 70 | mA | 2 | |||
| Power dissipation | PD | 500 | mW | 2 | |||
| Operating temperature | TA | 0 | 70 | ℃ | 2 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 2 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10 s | 2 | ||
| Operating supply voltage | VCC | 2 | 5 | 6 | V | 3 | |
| Input/output voltage | VIN、Vout | 0 | V | 3 | |||
| Input rise/fall time | tr、tf | 0 | 1000 | ns | VCC=2.0V | 3 | |
| Input rise/fall time | tr、tf | 0 | 500 | ns | VCC=4.5V | 3 | |
| Input rise/fall time | tr、tf | 0 | 400 | ns | VCC=6.0V | 3 | |
| High-level input voltage | VIH | 1.5 | V | VCC=2.0V; TA=25℃ | 3 | ||
| High-level input voltage | VIH | 3.15 | V | VCC=4.5V; TA=25℃ | 3 | ||
| High-level input voltage | VIH | 4.2 | V | VCC=6.0V; TA=25℃ | 3 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC=2.0V; TA=25℃ | 3 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC=4.5V; TA=25℃ | 3 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC=6.0V; TA=25℃ | 3 | ||
| High-level output voltage | VOH | 1.9 | V | VI=VIH or VIL; IOH=20μA; VCC=2.0V; TA=25℃ | 3 | ||
| High-level output voltage | VOH | 4.4 | V | VI=VIH or VIL; IOH=20μA; VCC=4.5V; TA=25℃ | 3 | ||
| High-level output voltage | VOH | 5.9 | V | VI=VIH or VIL; IOH=20μA; VCC=6.0V; TA=25℃ | 3 | ||
| High-level output voltage | VOH | 4 | 4.4 | V | VI=VIH or VIL; IOH=6.0mA; VCC=4.5V; TA=25℃ | 3 | |
| High-level output voltage | VOH | 5.5 | 5.9 | V | VI=VIH or VIL; IOH=7.8mA; VCC=6.0V; TA=25℃ | 3 | |
| Low-level output voltage | VOL | 0.1 | V | VI=VIH or VIL; IOL=20μA; VCC=2.0V; TA=25℃ | 3 | ||
| Low-level output voltage | VOL | 0.07 | 0.3 | V | VI=VIH or VIL; IOL=6.0mA; VCC=4.5V; TA=25℃ | 3 | |
| Low-level output voltage | VOL | 0.08 | 0.3 | V | VI=VIH or VIL; IOL=7.8mA; VCC=6.0V; TA=25℃ | 3 | |
| Input current | IIN | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V; TA=25℃ | 3 | |
| Output leakage current | IOZ | -5 | 5 | uA | VO=VCC or GND; VCC=6.0V; TA=25℃ | 3 | |
| Operating current | ICC | 0.2 | 10 | uA | VI=VCC or GND; IOUT=0μA; VCC=6.0V; TA=25℃ | 3 | |
| Operating voltage | VCC | 2 | 6 | V | 3 | ||
| Pulse duration, LE high | tW | 80 | ns | LE high; VCC=2V; CL=47pF, tr=tf≤20ns; Ta=25℃ | 4 |
CAD (KiCad official)
- Symbol:
74HC573S - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
74hc573s-etched.step/74hc573s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc573s.step/74hc573s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (9 pp, sha256
8bb9f87ce7a390e3, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).