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Contents

README

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LW5930N23C

Lewa Micro · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23

LW5930N23C from Lewa Micro, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the datasheet recommends separate VIN and VOUT ground planes that connect only at the GND pin.
2 VOUT power_out Regulated output voltage pin; connect a low-ESR capacitor of the nominal recommended value or larger from OUT to GND, and an internal pulldown discharges OUT when the regulator is in shutdown (VEN < VEN(LOW)).
3 VIN power_in Input pin, operating range 1.6V to 7.0V; use the recommended or larger ceramic capacitor from IN to ground, placed as close to the device as possible.

Key specifications

Parameter Value
Manufacturer Lewa Micro
Package SOT-23
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage VIN 1.6 7 V 5
Output Accuracy VOUT -1.5 1.5 % IOUT= 1mA 5
Current Limit ILIM 410 530 mA 5
Quiescent Current IQ 0.65 1 μA VIN= VEN= VOUT +1V, No Load 5
Line Regulation ΔVOUT/(ΔVIN*VOUT(NOM)) 0.1 0.3 %/V VIN= VOUT +1.0V to 7.0V, IOUT=1mA 5
Load Regulation ΔVOUT 30 70 mV 1mA≤IOUT≤400mA 5
VIN Supply Voltage (absolute maximum) VIN -0.3 9 V 4
EN Pin Voltage (absolute maximum) VEN -0.3 9 V 4
VOUT Pin Voltage (absolute maximum) VOUT -0.3 V Upper limit printed as VIN+0.3 4
ESD Susceptibility, HBM V(ESD) -4000 4000 V per ANSI/ESDA/JEDEC JS-001; printed ±4000 4
Junction Temperature Range (absolute maximum) TJ -40 150 ℃ 4
Storage Temperature Range TSTG -40 150 ℃ 4
Lead Temperature (Soldering) TSOLDER 260 ℃ 10s 4
VIN Supply Voltage (recommended) VIN 1.6 7 V 4
EN Pin Voltage (recommended) VEN 0 7 V 4
VOUT Pin Voltage (recommended) VOUT 0.8 5 V 4
Output Current (recommended) IOUT 0 400 mA 4
Junction Temperature Range (recommended) TJ -40 125 ℃ 4
Junction-to-ambient Thermal Resistance, SOT23 package RθJA 363 ℃/W Device mounted on FR-4 PCB, per JESD51-3 4

CAD (KiCad official)

  • Symbol: LW5930N23C
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: lw5930n23c-etched.step / lw5930n23c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lw5930n23c.step / lw5930n23c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lewa Micro datasheet (25 pp, sha256 53294d4f1daeb984, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF